AN2283 Freescale Semiconductor / Motorola, AN2283 Datasheet
AN2283
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AN2283 Summary of contents
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... Freescale Semiconductor, Inc. Application Note AN2283/D Rev. 0, 8/2002 Motorola Scalable Controller Area Network (MSCAN) Interrupts By: Shaila G. Konanahalli A.J. Pohlmeyer Field Application Engineers Detroit Sales Office Introduction This application note is intended to help the user understand the Motorola Scalable Controller Area Network (MSCAN) interrupts on HC08 and HC12 devices ...
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... Freescale Semiconductor, Inc. AN2283/D Wakeup Error Receive Transmit Wakeup Interrupt While the MSCAN is in Sleep Mode, it will wakeup when bus activity is detected. The central processor unit (CPU) requests the MSCAN to go into Sleep Mode after the bus traffic has been halted, typically signaled by a system-level sleep command message ...
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... Request) bit in the CMCR0 register CSWAI SYNCH Figure 1. MSCAN Module Control Register 0 (CMCR0 RWRNIF TWRNIF RERRIF Figure 2. MSCAN Receiver Flag Register (CRFLG) Go to: www.freescale.com AN2283/D Wakeup Interrupt Overview. Figure 1 and Figure Bit 0 TLNKEN SLPAK SLPRQ SFTRES 3 ...
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... Freescale Semiconductor, Inc. AN2283/D Transmit Structure Overview This subsection discusses the transmit structure on the MSCAN08 and MSCAN12. The MSCAN has three transmit buffers so that multiple messages can be set up for transmission onto the CAN bus. When more than one transmit message buffer is filled with a message, the local priority values in the corresponding Transmit Buffer Priority Register (TBPR) are compared to determine which message transmitted onto the bus first ...
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... ID25 ID20 ID19 ID18 SRR ID24 ID13 ID12 ID11 ID6 ID5 ID4 ID3 Figure 4. Extended Identifier Registers 1 = Extended format (29 bit Standard format (11 bit) Go to: www.freescale.com AN2283/D Transmit Structure Overview Bit 0 ID6 ID5 ID4 ID3 IDE Bit 0 ID24 ID23 ID22 ...
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... Freescale Semiconductor, Inc. AN2283/D RTR — Remote Transmission Request This flag defines the type of message frame that will be transmitted onto the CAN bus and whether or not that frame contains data. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. ...
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... ID strategy) to prevent this from possibly changing the intended priority of messages transmitted. Table 4. Transmit Header Table ID DLC Š to: www.freescale.com AN2283/D Transmit Structure Overview Table 4) can be implemented *Data_Pointer Highest Priority Message Lowest Priority Message 7 ...
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... Freescale Semiconductor, Inc. AN2283/D A structure can be created to refer to a particular row. The following example structure shows a standard identifier being used. /******* Transmit Header Table ***********/ typedef struct { volatile unsigned int ID: volatile unsigned char DLC: 4; volatile unsigned int *Data_Pointer; } Transmit_Header; Transmit_Header Transmission Process Overview Building on a good understanding of the transmit structure of the MSCAN, this subsection will address the transmitting process of the MSCAN ...
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... CTFLG.TXE1 = 0 CTFLG.TXE1 = 1 Transmit Buffer 2 Transmit Buffer 2 TX2 TX2 Message with Message with TBPR = 0x01 TBPR = 0x01 CTFLG.TXE2 = 0 CTFLG.TXE2 = 0 Go to: www.freescale.com AN2283/D Transmission Process Overview STAGE 4 (Transmit Buffer 0 transmits message) Transmit Buffer 0 TX0 Message with TBPR = 0x02 CTFLG.TXE0 = 0 Transmit Buffer 1 TX1 CTFLG.TXE1 = 1 ...
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... Freescale Semiconductor, Inc. AN2283/D Transmission The MSCAN Transmitter Flag Register (CTFLG) and the MSCAN Transmitter Process Control Register (CTCR) are relevant to the transmit process on the MSCAN. See Figure 7 Bit 7 0 NOTE: This CTFLG register is a special one. ABTAK2–ABTAK0 are status bits; ...
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... TXEIE that caused the interrupt in the CTCR. // Load the the message’s ID from the Transmit Table into the Transmit Buffer The priority is the index value to the message in the Transmit Table. Go to: www.freescale.com AN2283/D Transmission Process Overview 11 ...
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... Freescale Semiconductor, Inc. AN2283/D /* #asm LDAA #0x01; STAA $0x106; #endasm */ ctcrr.TXEIE0 = 1; //Enable the transmit interrupt for this buffer } // End of if (ctflg.TXE0 == 1) //Check to see if Transmit Buffer 1 is Empty else if(ctflg.TXE1 == 1){ ctcr.TXEIE1 = 0; //Disable the transmit interrupt that caused the interrupt tx_buffer1.ID0 = Tx_Table[index].ID; //Load the message’s ID from the Transmit Table into the Transmit Buffer tx_buffer1.DLC = Tx_Table[index].DLC ...
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... ID from the Transmit Table into the Transmit Buffer //Load the message’s DLC from the Transmit Table into the Transmit Buffer MSCAN Transmitter Flag Register (CTFLG) MSCAN Transmitter Control Register (CTCR) Go to: www.freescale.com AN2283/D Abort Process Overview 13 ...
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... Freescale Semiconductor, Inc. AN2283/D In the CTCR register there are the ABTRQ2, ABTRQ1, and ABTRQ0 bits which are the Abort Request bits corresponding to the three transmit buffers respectively. The user will need to set the appropriate ABTRQx bit to abort the message in the corresponding transmit buffer. ...
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... MSCAN when an abort of a message ABORT REQUEST ABTRQx = 1 LOSS OF ARBITRATION ABORT ABTAKx = 1 TRANSMISSION ENDS WITH ERRORS Figure 11. Abort Message Request Flowchart Go to: www.freescale.com AN2283/D Abort Process Overview THE MESSAGE IN BUFFER IS IN TRANSMISSION TRANSMISSION ENDS TRASMISSION COMPLETE WITH NO ERRORS NOTHING TO ABORT ...
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... Freescale Semiconductor, Inc. AN2283/D As seen in four separate scenarios: 1. When the message in the buffer is not undergoing transmission on the 2. When the message in the buffer is undergoing transmission on the bus The transmit interrupt routine may need to be modified to support the abort capability in the MSCAN. For example, when a transmit empty buffer is detected the service routine needs to signal the network/transport software layers if the transmission completed successfully or the message was aborted ...
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... Identifier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Go to: www.freescale.com AN2283/D Receive Structure Overview CPU SOFTWARE FILTERS (OPTIONAL BY THE USER) 17 ...
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... Freescale Semiconductor, Inc. AN2283/D Identifier Registers The Identifier Registers consists of either 11 bits (ID10–ID0) for the standard CAN 2.0 A/B format or 29 bits (ID28–ID0) for the extended CAN2.0 B format. See Figure 13 Identifier Register 0 (IDR0) Identifier Register 1 (IDR1) Identifier Register 2 (IDR2) Identifier Register 3 (IDR3) ...
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... Overview errors are found, the MSCAN acknowledges the receipt of this data frame by sending an ACK symbol onto the CAN bus. If errors are detected, the message is discarded and the MSCAN waits for the next message to be received. Go to: www.freescale.com AN2283/D Receive Structure Overview Data Byte Count DLC0 ...
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... Freescale Semiconductor, Inc. AN2283/D 2. The hardware identifier acceptance filters are applied to the successfully 3. When a message finds a filter match, the RxBG becomes the RxFG and Bit 7 0 Figure 15. MSCAN08 Identifier Acceptance Control Register (CIDAC) Bit 7 0 Figure 16. MSCAN12 Identifier Acceptance Control Register (CIDAC) IDAM1– ...
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... IDHIT0 to: www.freescale.com AN2283/D Receive Structure Overview Identifier Acceptance Hit Identifier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit 21 ...
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... Freescale Semiconductor, Inc. AN2283/D 4. After the RxBG is copied into the RxFG buffer, the RXF flag in the 5. When both the RxBG and RxFG buffers contain correctly received and Receive Interrupt To enable a receive interrupt, the Receiver Full Interrupt Enable (RXFIE) bit should be set in the MSCAN Receiver Interrupt Enable Register (CRIER). The receive buffer full (successful message reception) event (RXF = 1 in the CRFLG (MSCAN Receiver Flag Register)) will trigger a receive interrupt ...
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... For More Information On This Product RWRNIF TWRNIF RERRIF Figure 18. MSCAN Receiver Flag Register (CRFLG) 1 (set) = The receive buffer is full and a new message is available. 0 (clear) = The receive buffer is released (empty). Go to: www.freescale.com AN2283/D Receive Structure Overview Bit 0 TERRIF BOFFIF OVRIF RXF 23 ...
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... Freescale Semiconductor, Inc. AN2283/D Once again, the signals used in the CAN messages are stored in data structures which mirror the MSCAN receive buffers so that when storing data from the receive buffer all that is done is one for one data moves. In this case, the variable structure is called Store_RX. This format provides an efficient driver and improves execution time ...
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... The ACK Slot is in the Acknowledge field of the data frame. consists of and shows what is inside the Acknowledge field. MOTOROLA Motorola Scalable Controller Area Network (MSCAN) Interrupts For More Information On This Product, machine Figure 19 provides a reminder of what the data frame Go to: www.freescale.com AN2283/D Error Overview th 25 ...
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... Freescale Semiconductor, Inc. AN2283/D START ARBITRATION CONTROL OF FRAME FIELD FIELD Error Signaling When a node detects an error in transmission or reception, it signals the bus by transmitting an Error Flag. There are two kinds of error flags: • • These flags correspond to the error state of a node, which is governed by transmit and receive error counters ...
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... REC reset to 0 after 128 occurrences of 11 consecutive recessive [1] bits have been monitored on the bus. A minimum of 11 consecutive recessive [1] bits occur between messages (Acknowledgement Delimiter, End of Frame, and Intermission). Figure 20, there are a total of four states a node can enter Go to: www.freescale.com AN2283/D Error Interrupts Overview 27 ...
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... Freescale Semiconductor, Inc. AN2283/D TEC = 0 AND REC = 0 AFTER 128 OCCURRENCES OF 11 CONSECUTIVE RESSIVE [1] BITS ARE MONITORED 96 <= TEC < 128 OR 96 <= REC <128 NO WARNING/ERROR (NODE STATE: ERROR ACTIVE) TEC < 96 AND REC < 96 The node’s receiver has three states depending on the value of the REC: 1 ...
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... Receiver Error Interrupts are enabled to show examples of both scenarios. The MSCAN adjusts the REC value when receive errors are detected and when messages are received successfully. MOTOROLA Motorola Scalable Controller Area Network (MSCAN) Interrupts For More Information On This Product, Figure 22 illustrates generation of Receive Go to: www.freescale.com AN2283/D Error Interrupts Overview 29 ...
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... Freescale Semiconductor, Inc. AN2283/D BEGINNING OF THE APPLICATION CODE INITIALIZE CHIP (REC = TEC = 0) ENABLE RERRIE = 1 AND ENABLE RWRNIE = 1 ERROR INTERRUPTS RWRNIF = 1 READ THE CRFLG REGISTER (96 <= REC <128) RECEIVER WARNING INTERRUPT CLEAR RERRIF = 0 (SEE NOTES) SET RERRIE = 1 CLEAR RWRNIE = 0 IN THE CRIER REGISTER ...
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... Or, if the Receive Error Count was greater than 127, then it’ll be set to a value between 119 and 127 [If REC > 127, then 119 <= REC <= 127] Go to: www.freescale.com AN2283/D Error Interrupts Overview 128 <= REC < 255 RECEIVER ERROR PASSIVE 96 <= REC < 128 ...
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... Freescale Semiconductor, Inc. AN2283/D In summary, the REC increases by one for most RX errors, by eight on severe RX errors, and decrements by one on a successful RX. NOTE: More than one rule may apply during a given message transfer. Receiver Warning The Receiver Warning Interrupt tells the software driver that the node is in the Interrupt error active state, and the REC value is in the range 96 < ...
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... If RWRNIF = 0, then REC < 96, so set the Receiver Warning Interrupt Enable (RWRNIE) bit in CRIER to re-enable the Receiver Warning Interrupt RWRNIF = 1, then the node is still in the Receiver Warning State (REC >= 96 flowchart example illustrating generation of Transmit Warning, Go to: www.freescale.com AN2283/D Error Interrupts Overview Figure 23, 33 ...
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... Freescale Semiconductor, Inc. AN2283/D BEGINNING OF THE APPLICATION CODE ENABLE TERRIE = 1 AND ENABLE TWRNIE = 1 ERROR INTERRUPTS TWRNIF = 1 READ THE CRFLG (96 <= TEC <128) TRANSMITTER WARNING TRANSMITTER ERROR INTERRUPT CLEAR TERRIF = 0 CLEAR TWRNIF = 0 (SEE NOTES) SET TERRIE = 1 CLEAR TWRNIE = 0 CLEAR TERRIE = 0 IN THE CRIER REGISTER ...
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... So, any node can tolerate up to seven consecutive dominant [0] bits after sending an error flag. After detecting the 8 Go to: www.freescale.com AN2283/D Error Interrupts Overview TEC > 255 BUS OFF th ...
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... Freescale Semiconductor, Inc. AN2283/D 4. After a message transmits successfully, by getting an ACK and no error 5. The TEC is unchanged when: In summary, the TEC increases by eight for all TX errors and decrements by one on a successful TX. NOTE: More than one rule may apply during a given message transfer. Transmitter Warning ...
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... CRIER so that another Transmitter Error Passive Interrupt will not execute repeatedly for the duration of this state (transmitter error passive state). This is due to the fact that interrupt flags remain set in a level sensitive manner as long as the setting condition remains. Go to: www.freescale.com AN2283/D Error Interrupts Overview Figure 24, CRFLG utilizes the 37 ...
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... Freescale Semiconductor, Inc. AN2283/D To handle the Bus Off Interrupt source: 1. Clear the BOFFIF bit in CRFLG by writing it. (As mentioned in 2. Clear the Transmitter Error Interrupt Flag (TERRIF) bit in CRFLG by 3. Set the Soft Reset bit (soft reset state) in the Control Register 0 4 ...
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... If TWRNIF = 0, then REC < 96, so set the Transmitter Warning Interrupt Enable (TWRNIE) bit in CRIER to re-enable the Transmitter Warning Interrupt TWRNIF = 1, then the node is still in the Transmitter Warning State (REC >= 96). // Clear the RERRIF Flag in the CRFLG register Go to: www.freescale.com AN2283/D Error Interrupts Overview 39 ...
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... Freescale Semiconductor, Inc. AN2283/D Overrun Interrupt An Overrun Interrupt occurs when a new incoming message appears on the CAN bus when both the RxBG and RxFG buffers contain correctly received and filtered messages. To enable the Overrun Interrupt, set the OVRIE (Overrun Interrupt Enable) bit in CRIER which will result in an Overrun Interrupt when the OVRIF flag sets in CRFLG ...
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... Using the Motorola MSCAN Filter Configuration Tool (Motorola 13. MSCAN Low-Power Applications (Motorola document order number MOTOROLA Motorola Scalable Controller Area Network (MSCAN) Interrupts For More Information On This Product, number MC68HC08AZ60/D) MC68HC908AZ60/D) number MC68HC908AZ60A/D) document order number AN2010/D) AN2255/D) Go to: www.freescale.com AN2283/D References 41 ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2283/D Rev. 0 8/2002 Go to: www.freescale.com ...