CY2CC1810 Cypress Semiconductor, CY2CC1810 Datasheet

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CY2CC1810

Manufacturer Part Number
CY2CC1810
Description
1:10 Clock Fanout Buffer with Output Enable
Manufacturer
Cypress Semiconductor
Datasheet

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( DataSheet : www.DataSheet4U.com )
Cypress Semiconductor Corporation
Document #: 38-07055 Rev. *A
Features
Pin Description
Block Diagram
• Low-voltage operation
• V
• 1:10 fanout
• Drives either a 50-ohm or 75-ohm transmission line
• Over voltage tolerant input hot swappable
• Low input capacitance
• Low output skew
• Low propagation delay
• Typical (tpd < 4 ns)
• High-speed operation > 200 MHz
• LVTTL-/LVCMOS-compatible input
• Industrial versions available
• Packages available include: SOIC/SSOP
— Output disable to three-state
2,4,9,11,14,16,18,19,21,23
DD
1,7,8,12,13,17,20,24
range from 2.5 to 3.3V
IN
OE#
Pin Number
3,10,15,22
V D D
5
6
G N D
1:10 Clock Fanout Buffer with Output Enable
OUTPUT
3901 North First Street
Q10........Q1
(AVCMOS)
Pin Name
OE#
G
V
IN
ND
DD
Q 1
Q 2
Q 3
Q 4
Q 5
Q 7
Q 8
Q 9
Q 10
Q 6
Description
The Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1810 fanout buffer features one input and
ten three-state outputs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance-matching
series-damping resistors; they also reduce noise overall.
Pin Configuration
San Jose
GND
GND
GND
GND
VDD
VDD
OE#
Q10
Q9
Q8
Q7
IN
Ground
Power Supply
Output Enable
Input
Output
1
2
3
4
5
6
7
8
9
10
11
12
24 pin SOIC/SSOP
and
CA 95134
Pin Description
eliminate
COMLINK™ SERIES
24
23
22
21
20
19
18
17
16
15
14
13
Power
Power
LVTTL/LVCMOS
LVTTL/LVCMOS
AVCMOS
Revised May 7, 2002
www.DataSheet4U.com
CY2CC1810
the
GND
Q1
VDD
Q2
GND
Q3
Q4
GND
Q5
VDD
Q6
GND
408-943-2600
need
for

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CY2CC1810 Summary of contents

Page 1

... The Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress CY2CC1810 fanout buffer features one input and ten three-state outputs. Designed for data communications clock management appli- cations, the large fanout from a single input reduces loading on the input clock ...

Page 2

... Max., = (Max Min., = – GND = Max OUT V GND < 4.5V DD OUT Test Conditions OUT COMLINK™ SERIES CY2CC1810 + 0. 0. 0.5V DD Min. Typ. Max. 2.3 3.3 0.2 0 2.7V –1 = 0.5V 20 –0.7 –1.2 –50 100 80 Min. Typ. Max. 1.8 = – 1.6 5.8 0 ...

Page 3

... 2.0V/0.8V OUT The “point to point load circuit” 2.4V/0.0V F= 100 MHz 1.7V/0.7V OUT @ 3. 3.3V ± 5 – +85°C (See Figure Description COMLINK™ SERIES CY2CC1810 Min. Typ. Max fL= fMAX OE 0.63 DD fL=100 MHz OE# = GND 25 Min. Typ Max See Figure 8 ...

Page 4

... Figure 4. Voltage Waveforms–Propagation Delay Times Output Control (low-level enabling) 2.5 V 1.25 V Waveform VDD 2.5 V 1.25 V Waveform Table 1. 500 ohm t PLH t t PHZ COMLINK™ SERIES CY2CC1810 Min. Typ. See Figure 4 1.5 3.8 1.5 3.8 See Figure See Figure 4 0.4 0.6 See Figure 11 See Figure 13 1. PLH 1 ...

Page 5

... V Waveform 2 500 ohm Table 2. t PLH t t PHZ t PLH l l tsk = (P) PHL PLH Figure 11. Pulse Skew–tsk COMLINK™ SERIES CY2CC1810 1 PLH 1.5 V Figure 9. Voltage Waveforms– [15] Propagation Delay Times VOH (min) 1 PZL Z 1 PZH V 1. GND Z Figure 10. Voltage Waveforms– ...

Page 6

... INPUT OUTPUT 1 OUTPUT 2 PACKAGE 1 OUTPUT PACKAGE 2 OUTPUT Ordering Information Part Number CY2CC1810SI CY2CC1810SIT CY2CC1810OI CY2CC1810OIT CY2CC1810SC CY2CC1810SCT CY2CC1810OC CY2CC1810OCT Document #: 38-07055 Rev PHL1 PLH1 tsk ( PLH 2 PLH tsk = (P) PLH 2 PLH1 PHL2 Figure 12. Output Skew–tsk (0) INPUT ...

Page 7

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24-lead (300-mil) Molded SOIC S13 COMLINK™ SERIES CY2CC1810 51-85025-A 51-85078-** Page ...

Page 8

... Document Title: CY2CC1810 1:10 Clock Fanout Buffer with Output Enable Document #: 38-07055 REV. ECN NO. Issue Date ** 107080 06/07/01 *A 114316 05/08/02 Document #: 38-07055 Rev. *A Orig. of Change Description of Change IKA Convert from IMI to Cypress format TSM I validation DD COMLINK™ SERIES CY2CC1810 Page ...

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