CY2DL1504 Cypress Semiconductor, CY2DL1504 Datasheet
CY2DL1504
Related parts for CY2DL1504
CY2DL1504 Summary of contents
Page 1
... CY2DL1504 low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between LVPECL or LVDS input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The output enable function allows the outputs to be asynchronously driven to a high-impedance state ...
Page 2
... Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information........................................................ 9 Ordering Code Definition............................................. 9 Package Diagram............................................................ 10 Acronyms ........................................................................ 11 Document Number: 001-56312 Rev. *F Document Conventions ................................................. 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 CY2DL1504 Page [+] Feedback ...
Page 3
... Pinout Figure 1. Pin Diagram – CY2DL1504 20-Pin TSSOP Package Table 1. Pin Definitions Pin No. Pin Name 1,9,13 V Power SS 2 CLK_EN Input 3 IN_SEL Input 4 IN0 Input 5 IN0# Input 6 IN1 Input 7 IN1# Input 8 OE Input 10,18 V Power DD 11,14,16,19 Q(0:3)# Output 12,15,17,20 Q(0:3) Output Document Number: 001-56312 Rev ...
Page 4
... Condition Nonfunctional Nonfunctional SS Nonfunctional SS Nonfunctional JEDEC STD 22-A114-B At 1/8 in. Condition 2.5-V supply 3.3-V supply Commercial Industrial Power-up time for V DD reach minimum specified voltage. (Power ramp must be monotonic) CY2DL1504 Min Max Unit –0.5 4.6 V –0.5 Lesser of 4 0.4 DD –0.5 Lesser of 4 0.4 DD –55 150 ° ...
Page 5
... Q and Q# pairs [ TERM 0.75V – 1.75V SS, OUT CLK_EN has pull-up only IN_SEL has pull-down only OE has pull-up only Measured at 10 MHz; per pin minimum of greater than 200 mV. ID CY2DL1504 Min Max Unit – – 0 –0.3 – ...
Page 6
... Input rise/fall time < 1.5 ns (20% to 80%) Measured at 1 GHz. Synchronous clock enable – (CLK_EN) switched low Synchronous clock enable – (CLK_EN) switched high CY2DL1504 Typ Max Unit – 1.5 GHz – 1.5 GHz – 480 ps – – ...
Page 7
... Q Q Document Number: 001-56312 Rev. *F Figure 2. LVDS Output Termination Z=50 Q 100 Z= Figure 6. Output Duty Cycle PERIOD ODC t PERIOD CY2DL1504 )/2 ICM )/2 A OCM A B Δ – OCM OCM1 OCM2 B ...
Page 8
... SK1 D Figure 8. RMS Phase Jitter Phase noise Offset Frequency f2 f1 RMS Jitter ∝ Area Under the Masked Phase Noise Plot Figure 9. Output Rise/Fall Time 80% 80% 20 Figure 10. Synchronous Clock Enable Timing CY2DL1504 Phase noise mark SOE Page [+] Feedback ...
Page 9
... Temperature range C = Commercial I = Industrial Pb-free TSSOP package Number of differential output pairs Base part number Company ID Cypress CY2DL1504 Production Flow Commercial, 0 ° °C Commercial, 0 ° °C Industrial, –40 ° °C Industrial, –40 ° °C Page [+] Feedback ...
Page 10
... Package Diagram Figure 11. 20-Pin Thin Shrunk Small Outline Package (4.40 mm Body) ZZ20 Document Number: 001-56312 Rev. *F CY2DL1504 51-85118 *C Page [+] Feedback ...
Page 11
... Celsius dBc decibels relative to the carrier GHz giga hertz Hz hertz kΩ kilo ohm µA micro amperes µF micro Farad µs micro second mA milliamperes ms millisecond mV millivolt MHz megahertz ns nano second Ω ohm pF pico Farad ps pico second V volts W watts CY2DL1504 Page [+] Feedback ...
Page 12
... Document History Page Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision ECN Orig. of Change ** 2782891 CXQ *A 2838613 CXQ *B 3010332 CXQ Document Number: 001-56312 Rev. *F Submission Description of Change Date 10/09/09 New Datasheet. 01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”. ...
Page 13
... Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision ECN Orig. of Change *C 3090644 CXQ *D 3135189 CXQ *E 3090938 CXQ *F 3208968 CXQ Document Number: 001-56312 Rev. *F Submission Description of Change Date 11/19/2010 Changed V and V specs from 4.0V to “lesser of 4 ...
Page 14
... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-56312 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 29, 2011 CY2DL1504 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...