CY2DL1504 Cypress Semiconductor, CY2DL1504 Datasheet - Page 6

• Manufacturer Part Number: CY2DL1504
• Description: 1:4 Differential LVDS Fanout Buffer
• Manufacturer: Cypress Semiconductor

AC Electrical Specifications
(V
Document Number: 001-56312 Rev. *F
F
F
t
t
t
t
PN
t
t
t
t
Notes
PD
ODC
SK1
SK1 D
JIT
R
SOD
SOE
8. Refer to
9. Refer to
10. Refer to
11. Refer to
12. Refer to
IN
OUT
DD
, t
[8]
ADD
[11]
Parameter
F
[10]
[9]
[12]
= 3.3 V ± 5% or 2.5 V ± 5%; T
[10]
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
on page 7.
on page 7.
on page 8.
on page 8.
on page 8.
Input frequency
Output frequency
Propagation delay input pair to output
pair
Output duty cycle
Output-to-output skew
Device-to-device output skew
Additive RMS phase noise
156.25 MHz Input
Rise/fall time < 150 ps (20% to 80%)
V
Additive RMS phase jitter (Random)
Output rise/fall time, single-ended
Time from clock edge to outputs
disabled
Time from clock edge to outputs
enabled
ID
> 400 mV
Description
A
= 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
F
Input rise/fall time < 1.5 ns
(20% to 80%)
Diff input at 50% duty cycle
Frequency range up to 1 GHz
Any output to any output, with
same load conditions at DUT
Any output to any output
between two or more devices.
Devices must have the same
input and have the same output
load.
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 1 MHz
Offset = 10 MHz
Offset = 20 MHz
156.25 MHz, 12 kHz to 20 MHz
offset; input rise/fall time <
150 ps (20% to 80%), V
400 mV
50% duty cycle at input,
20% to 80% of full swing
(V
Input rise/fall time < 1.5 ns
(20% to 80%)
Measured at 1 GHz.
Synchronous clock enable
(CLK_EN) switched low
Synchronous clock enable
(CLK_EN) switched high
OUT
OL
to V
= F
IN
OH
Condition
)
ID
>
Min
DC
DC
48
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY2DL1504
–120
–135
–135
–150
–154
–155
Max
0.11
480
150
300
700
700
1.5
1.5
52
30
Page 6 of 14
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
GHz
GHz
Unit
ps
ps
ps
ps
ps
ps
ps
%
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