CY2DP1502 Cypress Semiconductor, CY2DP1502 Datasheet - Page 12

• Manufacturer Part Number: CY2DP1502
• Description: 1:2 LVPECL Fanout Buffer
• Manufacturer: Cypress Semiconductor

Document History Page
Document Number: 001-56308 Rev. *G
Revision
Document Title: CY2DP1502 1:2 LVPECL Fanout Buffer
Document Number: 001-56308
*G
*A
*B
*C
*D
*E
*F
**
3234654
2838916
3017258
3100234
3137726
2782891
3011766
3137726
ECN
Change
Orig. of
VED
CXQ
CXQ
CXQ
CXQ
CXQ
CXQ
CXQ
Submission
01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”.
08/20/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page
08/27/2010 Corrected Output Rise/Fall time diagram.
11/18/2010 Updated Phase jitter to 0.15ps max from 0.11ps max.
01/13/2011 Removed “Preliminary” status heading.
01/13/2011 Rev’ed and posted
10/09/09
04/19/2011 Minor change, no content change.
Date
New Datasheet.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in t
Added t
Change V
- 1.15V to V
Removed V
Added R
= 140 k.
Added a measurement definition for C
page 3.
Added V
mV for DC - 150 MHz and min = 400 mV for 150 MHz to 1.5 GHz.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 4 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 4.
Added condition to t
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
3, 4, 5, 6 and 8, to be consistent with EROS.
1 and in t
Added note 3 to describe I
Removed reference to data distribution from “Functional Description”.
Changed R
Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the
DC Electrical Specs table.
Added max V
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical
Specs table.
Added “Frequency range up to 1 GHz” condition to t
Updated package diagrams.
Added Acronyms and Ordering Code Definition.
Changed V
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Removed R
Changed C
Changed PN
Removed resistors on IN/IN# from
PU
P
PP
JIT
JIT
OH
spec in the DC Electrical Specs table on page 3. Min = 60 k, Max
spec to the Operating Conditions table on page 2.
P
IN
IN
spec to the AC Electrical Specs table on page 4. V
OD
DD
P
in the AC Electrical Specs table on page 4.
in the AC Electrical Specs table.
ADD
for differential inputs from 100 k to 150 k in the Logic Block
in the DC Electrical Specs table on page 3: minimum from V
ID
and V
spec for differential input clock pins IN
condition to “Measured at 10 MHz”.
- 1.20V; maximum from V
spec from the DC Electrical Specs table on page 3.
of 1.0V in DC Electrical Specs table.
specs for 1MHz, 10MHz, and 20MHz offsets.
OUT
R
and t
specs from 4.0V to “lesser of 4.0 or V
Description of Change
IH
F
specs in the AC Electrical specs table on page 4
and I
IL
Logic Block
specs.
IN
in the DC Electrical Specs table on
DD
- 0.75V to V
Diagram.
X
ODC
and IN
DD
spec.
CY2DP1502
- 0.70V.
X
DD
#.
PP
Page 12 of 13
+ 0.4”
min = 600
DD