CY2DP1502 Cypress Semiconductor, CY2DP1502 Datasheet - Page 3

• Manufacturer Part Number: CY2DP1502
• Description: 1:2 LVPECL Fanout Buffer
• Manufacturer: Cypress Semiconductor

Pinouts
Table 1. Pin Definitions
Absolute Maximum Ratings
Operating Conditions
Document Number: 001-56308 Rev. *G
1,3
2,4
5
6
7
8
V
V
V
T
ESD
L
UL–94
MSL
V
T
t
Note
PU
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
U
A
S
DD
IN
OUT
DD
Pin Number
Parameter
Parameter
[2]
HBM
[2]
Supply voltage
Input voltage, relative to V
DC output or I/O voltage, relative to V
Storage temperature
Electrostatic discharge (ESD) protection
(Human body model)
Latch up
Flammability rating
Moisture sensitivity level
Q(0:1)
Q(0:1)#
V
IN#
IN
V
Supply voltage
Ambient operating temperature
Power ramp time
SS
DD
Pin Name
Figure 1. Pin Diagram – 8-Pin SOIC and 8-Pin TSSOP Package
Description
Description
Output
Output
Power
Input
Input
Power
SS
Pin Type
Q0#
Q1#
Q1
Q0
SS
1
2
3
4
Nonfunctional
Nonfunctional
At 1/8 in
Nonfunctional
Nonfunctional
JEDEC STD 22-A114-B
LVPECL complementary output clocks
2.5-V supply
3.3-V supply
Commercial
Industrial
Power-up time for V
minimum specified voltage (power
ramp must be monotonic).
LVPECL output clocks
Ground
LVPECL complementary input clock
LVPECL input clock
Power supply
8
7
6
5
Condition
Condition
V
IN
IN#
V
DD
SS
DD
to reach
Description
Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test
2000
–0.5
–0.5
–0.5
2.375
3.135
Min
–55
0.05
Min
–40
0
lesser of 4.0
or V
lesser of 4.0
or V
CY2DP1502
V-0
3
Max
2.625
3.465
150
4.6
DD
DD
Max
500
–
70
85
+ 0.4
+ 0.4
Page 3 of 13
Unit
Unit
°C
V
V
ms
V
V
°C
°C
V
V