CY2DP3110 Cypress Semiconductor, CY2DP3110 Datasheet - Page 9

• Manufacturer Part Number: CY2DP3110
• Description: Differential Clock/Data Fanout Buffer
• Manufacturer: Cypress Semiconductor

Document #: 38-07469 Rev.*G
Document History Page
Document Title: CY2DP3110 FastEdge™ Series 1 of 2:10 Differential Clock/Data Fanout Buffer
Document Number: 38-07469
REV.
*C
*D
*G
*A
*B
*E
*F
**
ECN NO. Issue Date
121284
126251
127696
128731
130299
227708
229393
247626
See ECN
See ECN
See ECN
11/12/02
04/15/03
06/12/03
08/04/03
11/19/03
RGL/GGK Changed the max. Dissipation, Junction to ambient from 100 to 70°C/W
RGL/GGK Provided data for TBD’s to match the device
RGL/GGK Changed V
Change
Orig. of
RGL
RGL
RGL
RGL
RGL
New Data Sheet
Added VBB in the block diagram
Corrected specs that does not match EROS/IROS
Changed V
Shifted table on ECL levels to match PECL
Added power-up requirements to absolute maximum conditions
Changed title (ComLink to FastEdge)
Changed operation value from 3.0 GHz to 1.5 GHz in features
Modified Note 21: reduced swing value from up to 3 GHz to 2.2 GHz
Specified TTB value from TBD to 250 ps
Specified Vo (pp) values from TBDs to 0.34 ps(min) at < 1.5 GHz, 0.30 ps
(typ) at 2.2 GHz
Changed Jitter value from 10 ps to 1 ps (intrinsic)
Corrected the “VCCO” to “VCC” in the Pin Configuration diagram.
Added Junction Temperature(T
Replaced I
CC
OHMIN
OH
calculation with power calculation in the footnote
and V
in PECL Output table to V
OL
to match the Char Data
Description of Change
J
) parameter of 150°C max
FastEdge™ Series
CC
-1.2V
CY2DP3110
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