AN2333 Freescale Semiconductor / Motorola, AN2333 Datasheet
AN2333
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AN2333 Summary of contents
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... Freescale Semiconductor, Inc. Application Note AN2333/D Rev. 0, 10/2002 Maximizing the Performance of Two Fast Ethernet Links on MSC8101 FCCs by Philippe Chartier This application note describes how to implement a dual full-duplex Fast Ethernet driver on the MSC8101ADS board. It examines the on-board Ethernet transceiver configuration and the fast communication controller (FCC) Ethernet configuration on the MSC8101 ...
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IEEE 802.3 Ethernet Basics 1.1 Ethernet Transceiver In most systems, the Ethernet medium is accessed from the controller through an Ethernet transceiver. This section discusses how the Ethernet transceiver on the MSC8101ADS is configured and also describes the bus interface ...
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Freescale Semiconductor, Inc. 1.2 Media Independent Interface (MII) There are different interconnect bus formats for interfacing Ethernet controllers and transceivers, such as MII, reduced media independent interface (RMII), and serial media independent interface (SMII). The MSC8101 FCCs use the MII ...
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IEEE 802.3 Ethernet Basics Port Line Port B15 (PA17) Port B16 (PA16) Port B17 (PA15) Port B18 (PA14) Port B02 (PA30) Port B01 (PA31) Port C12 (D20) Port C13 (D19) 1.3 MSC810ADS FCCs Running Ethernet The MSC8101 communications processor module ...
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Freescale Semiconductor, Inc. Ethernet Link 2 2FCCs Project This section describes the hardware set-up and the software modules of the 2FCCs project. 2.1 Hardware Set-up There are two example hardware configurations for the 2FCCs project. The first uses two MSC8101ADS ...
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Project MSC8101ADS FCC2 NOTE: The Ethernet link is Figure 3. Set-up Using Two MSC8101ADS Boards 2.1.2 MSC8101ADS and ECOM Set-up The MSC8101ADS-ECOM set-up is preferable to the two-MSC8101ADS set-up because it allows the MSC8101 device to handle two fast ...
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Freescale Semiconductor, Inc. 2.2 Software Modules Signal MII TX_ER MII RX_DV MII TX_EN MII RX_ER MII COL MII CRS NBL TXD3 NBL TXD2 NBL TXD1 NBL TXD0 NBL RXD0 NBL RXD1 NBL RXD2 NBL RXD3 CLK2 CLK1 PC13 PC12 HRESET ...
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Project The 2FCCs project was developed using Metrowerks® CodeWarrior® 1.5 for Windows. However compiler independent and therefore runs on any suitable IDE. Moreover, the project is host-independent and can run Solaris, Linux, ...
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Freescale Semiconductor, Inc. 2.2.4 Interrupt controller The interrupt controller used here is basic, but it performs all the required tasks: context saving, interrupt source determination, interrupt handler address match plus execution, and context restoring. Before the MSC8101 device enters normal ...
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Performance • Timer.h. Reflects the value of the on-board crystal: #define DIV16 #define BRG_VALUE 306 • Payload.h. Sets the frame size: #define FRAME_SIZE_1 64 #define FRAME_SIZE_2 64 • FCCs_Int_Handler.h. Uses the hand-optimized ASM (reduced register set version: #define ...
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Freescale Semiconductor, Inc. because read or write requests must cross the Q2PPC bridge and the system bus/local bus bridge. This requirement directly affects MSC8101 internal bus loading and global system speed, as well as all memory space to be accessed ...
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Performance 3.3 Buffer Descriptors set of structures containing information on the buffer size, status, properties, and pointers. BDs provide the means to manage buffers. The CPM/FCC reads and writes to BDs via SDMA transfers that are ...
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Freescale Semiconductor, Inc. The ISR decision logic is implemented through either the SIU Interrupt Vector Register (SIVEC) or through the SIU Interrupt Pending Register (SIPNR_H and SIPNR_L), as follows: • SIVEC. This register contains a 6-bit code representing the unmasked ...
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Results and Conclusions 3.6 Timer and Statistics In its default configuration, the 2FCC project works with a reduced context switching ISR in conjunction with an ASM FCC interrupt handler. However, the timer interrupt handler is not written in ASM and ...
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Freescale Semiconductor, Inc. interrupt, itself due to the basic buffer management. As expected, the interrupt frequency increases when frame size decreases. This demonstrates the need for care in both the interrupt controller and FCC interrupt handler design. The results obtained ...
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CPM Performance Tool 3. Set the speed, buffer size and other parameters for both FCC1 and FCC2. 16 Freescale Semiconductor, Inc. Figure 7. CPM Performance Tool, Screen 2 Figure 8. CPM Performance Tool, Screen 3 For More Information On This ...
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Freescale Semiconductor, Inc. 4. Directly watch the results or save them into a text file. Figure 9. CPM Performance Tool, Screen 4 The assumptions underlying the 2FCCs project settings are as follows: • CPM bus access schemes: — System bus ...
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Related Reading Speed Configuration Frame Size (Bytes) 1000 1500 6 Related Reading [1] MSC8101 Reference Manual, MSC8101RM/D, available at the website shown on the back cover of this document. [2] MSC8101ADS User’s Manual, available at the website shown on the ...
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Freescale Semiconductor, Inc. NOTES: For More Information On This Product, Go to: www.freescale.com Related Reading 19 ...
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... StarCore are trademarks of Motorola, Inc. Metrowerks and CodeWarrior are registered trademarks of Metrowerks Corp. in the U.S. and/or other countries. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2333/D For More Information On This Product, Go to: www.freescale.com ...