AN2333 Freescale Semiconductor / Motorola, AN2333 Datasheet - Page 12

• Manufacturer Part Number: AN2333
• Description: Maximizing the Performance of Two Fast Ethernet Links on MSC8101 FCCs
• Manufacturer: Freescale Semiconductor / Motorola

Performance
3.3 Buffer Descriptors
3.4 Interrupt Service Routine
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A BD is a set of structures containing information on the buffer size, status, properties, and pointers. BDs
provide the means to manage buffers. The CPM/FCC reads and writes to BDs via SDMA transfers that
are transparent to the user. BD rings should be located in internal SRAM because they do not consume
much memory and they allow flexibility in buffer servicing methods for the FCC interrupt handler.
Locating BDs in external SDRAM decreases system performance without offering any advantages.
Locating BDs in internal DPRAM may offer the advantage of low interrupt frequency, but accesses to
DPRAM increase SC140 core cycle consumption and latency. Also, locating BDs in internal DPRAM
has an impact on the RSTATE in the FCC common parameters. As noted in Section 3.2, BD rings should
be 4-byte aligned.
The transmit buffer descriptor INT bit is set in one of three ways, and the setting has a direct impact on
the interrupt frequency and thus on the system global performance:
• Set for each transmit buffer. As soon as a smart buffer management or buffer queuing system is
• Set for the last buffer of the transmit ring, which is suitable for basic systems.
• Set for none, which simplifies the design of the FCC interrupt handler.
The receive buffer descriptor INT bit is set in one of three ways:
• Set for each receive buffer. As soon as a smart buffer management or buffer queuing system is
• Set for the last buffer of the receive ring, which is suitable for basic systems.
• Set for none: polling. In systems in which the main task is intensive and repetitive (such as traffic
Note:
An interrupt service routine (ISR) runs when the SIU-CPM interrupt controller (SIC) generates an
interrupt. The ISR determines the resource(s) responsible for the interrupt and launches the appropriate
resource interrupt handler. The routine is encapsulated by context saving and restoring functions. Context
switching can be either complete or reduced, as follows:
• Complete. In normal conditions, complete register context saving/restoring consumes 56 cycles.
• Reduced. In the 2FCCs project, the number of cycles was decreased to 26 by saving/restoring registers
The choice between reduced or complete context switching has a direct impact on the Ethernet frame
latency and on the real-time aspects of the global system. Context switching is a great source of errors, so
care must be taken in designing this module. Other important aspects of ISRs that warrant consideration
at design time are reentrance and whether the ISR is edge or level triggered.
implemented, this choice is a must. The 2FCCs project uses this option in order to count transmitted
frames.
implemented, this choice is a must.
aggregation), polling received buffers can be advantageous. The interrupt mechanism is then no longer
mandatory, but a system scheduler must be implemented.
(r[0–7] and d[0–7]).
Once the BD that points to a buffer is is full or not empty (for transmit buffers) or empty or not
fully (for receive buffers), neither the SC140 core nor any MSC8101 peripherals should write or
even read the contents of the buffer. Doing so may result in a crash and freeze of the CPM
and/or SC140 core.
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