AN2333 Freescale Semiconductor / Motorola, AN2333 Datasheet - Page 8

• Manufacturer Part Number: AN2333
• Description: Maximizing the Performance of Two Fast Ethernet Links on MSC8101 FCCs
• Manufacturer: Freescale Semiconductor / Motorola

2FCCs Project
2.2.1 Board Initialization
2.2.2 Ethernet Transceiver (PHY) Initialization
2.2.3 FCC Driver Initialization
8
The 2FCCs project was developed using Metrowerks® CodeWarrior® 1.5 for Windows. However, it is
compiler independent and therefore runs on any suitable IDE. Moreover, the project is host-independent
and can run on a PC or on Solaris, Linux, and so on. When the project is compiled, it should generate
neither errors nor warnings. The executable file can be downloaded and run on the MSC8101ADS, where
it can enter Debug mode and run step-by-step.
Before the executable image is downloaded, the MSC8101ADS must be initialized via a command script
in the BIN directory. This script disables the watchdog timer and configures the memory controller,
enabling memory accesses. Then the 2FCCs binary image is downloaded into the MSC8101ADS
memory. In the example discussed here, it is downloaded into the MSC8101 internal SRAM. Then the
SC140 core executes the bootstrap code (provided by the compiler) until the start of the main function. At
this point, the program starts by setting all the parallel ports to act as GPIO inputs, resetting the CPM, and
initializing the interrupt controller.
The payloads are dummy Ethernet frames, which contain source and destination MAC addresses, frame
length, and random payload. The frame size is determined at compile time, and the FCCs transmit it over
the Ethernet link.
PHY initialization is performed twice, one for each Ethernet transceiver, as follows:
1. Two CPM GPIO signals are configured to act as
2. According to the input parameters, the code configures each FCC for 10 or 100 Mbps speed, half- or
3. As output, the link status is returned and, if relevant, the results of the auto-negotiation.
FCC driver initialization is performed twice, once for each FCC. This process configures the FCC to
work in Ethernet mode by programming the following parameters:
1. Configure the external CPM to act as an Ethernet modem.
2. Configure the General FCC Mode Registers (GFMRx), which define all options common to the FCC,
3. Set the FCC clock route.
4. Enable RMON frame counters for statistics and throughput calculation.
5. Specify the events on which the FCCs trigger an interrupt.
6. Connect the FCC interrupt handler to the interrupt controller.
7. Initialize and allocate buffers and buffer descriptor memory.
The code configures the FCC to work in Promiscuous mode, but the mode may need to be changed if the
code is reused.
In this set-up the
full-duplex operation, or auto-negotiation mode.
regardless of the protocol and select the channel protocol mode.
In this case, the Ethernet protocol is selected: GFMRx[Mode2] = 1100).
Tx and Rx clocks are provided by the Ethernet transceivers and internally routed to the correct FCC.
Freescale Semiconductor, Inc.
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MDC
and
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MDIO
signals are common for the two Ethernet transceivers.
MDC
and
MDIO
signals.