CY2SSTV857-27 Cypress Semiconductor, CY2SSTV857-27 Datasheet - Page 4

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CY2SSTV857-27

Manufacturer Part Number
CY2SSTV857-27
Description
Differential Clock Buffer/Driver DDR333/PC2700-Compliant
Manufacturer
Cypress Semiconductor
Datasheet
www.DataSheet4U.com
Document #: 38-07464 Rev. *G
CLK#
CLK
CLK#
represents a capacitive load
CLK
represents a capacitive load
DDR-SDRAM
DDR _SDRAM
Output load capacitancce for 4 DDR-SDRAM Loads: 10 pF < CL < 16 pF
Yx
Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF
120 Ohm
120 Ohm
120
Ohm
120
Ohm
PLL
FBIN
FBIN#
Figure 3. Cycle-to-cycle Jitter
Figure 4. Clock Structure # 1
Figure 5. Clock Structure # 1
PLL
FBIN
FBIN#
t
C(n)
FBOUT#
FBOUT#
FBOUT
FBOUT
= 2.5"
= 2.5"
0.3"
t
0.3"
C(n+1)
= 0.6" (Split to Terminator)
= 0.6" (Split to Terminator)
DDR-SDRAM
DDR-SDRAM
DDR-SDRAM
DDR-SDRAM
SDRAM
SDRAM
DDR -
DDR -
VTR
VCP
VCP
VTR
CY2SSTV857-27
DDR-SDRAM
DDR-SDRAM
Stack
Stack
120 Ohm
120
Ohm
Page 4 of 9

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