CY2SSTV857-27 Cypress Semiconductor, CY2SSTV857-27 Datasheet - Page 6

• Manufacturer Part Number: CY2SSTV857-27
• Description: Differential Clock Buffer/Driver DDR333/PC2700-Compliant
• Manufacturer: Cypress Semiconductor

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Document #: 38-07464 Rev. *G
Absolute Maximum Conditions
Input Voltage Relative to V
Input Voltage Relative to V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: .................................... 0°C to +85°C
Maximum Power Supply: ................................................3.5V
DC Electrical Specifications
AC Electrical Specifications
V
V
V
V
V
I
I
I
V
V
V
V
I
I
I
I
Cin
f
t
t
D
t
Notes:
Parameter
10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 50 kHz with a down
11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
12. Refers to transition of non-inverting output.
IN
OL
OH
OZ
DDQ
DD
DDS
CLK
DC
LOCK
tsl(o)
PZL
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Unused inputs must be held HIGH or LOW to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary
5. Differential cross-point input voltage is expected to track V
6. For load conditions see Figure 6.
7. The value of V
8. All outputs switching load with 14 pF in 60Ω environment. See Figure 6.
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
Parameter
DDQ
IL
IH
ID
IX
OL
OH
OUT
OC
TYC
input level. See Figure 6.
spread or –0.5%.
where the cycle time (t
, t
PZH
Supply Voltage
Input Low Voltage
Input High Voltage
Differential Input Voltage
Differential Input Crossing
Voltage
Input Current [CLK, FBIN, PD#] V
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
Output Crossing Voltage
High-Impedance Output Current V
Dynamic Supply Current
PLL Supply Current
Standby Supply Current
Input Pin Capacitance
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Duty Cycle
Output Clocks Slew Rate
Output Enable Time
OC
is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 6.
[5]
C
) decreases as the frequency goes up.
Description
[11]
SS
DDQ
:...............................V
or AV
Description
[6]
[12]
DD
(AV
(AV
[4]
[7]
[8]
(all outputs)
: ........... V
[2]
DD
DD
= V
= V
Operating
PD#
CLK, FBIN
CLK, FBIN
V
V
V
V
All V
V
PD# = 0 and CLK/CLK# < 10 MHz
IN
DDQ
DDQ
DDQ
DDQ
O
DDA
DDQ
DDQ
DDQ
DDQ
= GND or V
= 0V or V
DDQ
SS
= 2.375V, I
= 2.375V, V
= 2.375V, V
= 2.375V, I
only
= 2.5v ± 5%, T
= 2.5V±5%, T
and is the voltage at which the differential signal must be crossing.
– 0.3V
+ 0.3V
, F
Condition
O
IN
= 170 MHz
O
= V
AV
60 MHz to 100 MHz
101 MHz to 170 MHz
20%–80% of VOD
OL
OH
= V
OUT
OUT
DD
DDQ
= 12 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
range:
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
A
= –12 mA
DDQ
A
SS
, V
= 0°C to +85°C)
= 1.2V
= 1V
= 0°C to +85°C)
DDQ
< (V
Condition
in
= 2.5V ± 0.2V
or V
(V
(V
out
0.7 × V
DDQ
DDQ
) < V
[9, 10]
Min.
2.38
0.36
[3]
–10
–28
–10
1.7
1.1
26
/2) – 0.2 V
/2) – 0.2 V
SS
DDQ
in
DDQ
and V
or V
.
DDQ
Min.
49.5
60
40
49
out
1
Typ.
DDQ
DDQ
–32
235
CY2SSTV857-27
2.5
).
35
should be constrained to the
9
/2 (V
/2 (V
Typ.
50
3
0.3 × V
V
V
DDQ
DDQ
DDQ
DDQ
Max.
2.63
300
100
0.6
10
10
12
/2) + 0.2
/2) + 0.2
4
+ 0.3
Max.
– 0.4
50.5
200
100
DDQ
60
51
25
2
Page 6 of 9
WHC
Unit
MHz
V/ns
Unit
mA
mA
mA
mA
µA
µA
µA
pF
µs
ns
%
%
%
V
V
V
V
V
V
V
V
V
/t
C
,