AN2372 Freescale Semiconductor / Motorola, AN2372 Datasheet - Page 11

• Manufacturer Part Number: AN2372
• Description: Using the Output Compare TPU Function (OC) with the MPC500Family
• Manufacturer: Freescale Semiconductor / Motorola

6
The CPU configures the OC function as follows:
The CPU should monitor the HSR register (or the channel interrupt) until the TPU clears the service request
to 00 before changing parameters or issuing a new service request to this channel.
In the host-initiated pulse mode, the CPU configures CHANNEL_CONTROL, OFFSET, and
REF_ADDR1 and initiates the match event to be scheduled by issuing an HSR%01. When the HSR is
serviced, locations 0xEC and 0xEE are updated with the current values of TCR1 and TCR2, respectively,
and the scheduled match event is loaded into the event register. When the scheduled match event occurs, the
actual match time is loaded into ACTUAL_MATCH_TIME and an interrupt is requested. If host sequence
bit 1 is set, only the update of locations 0xEC and 0xEE with TCR1 and TCR2, respectively, occurs and the
function terminates after requesting an interrupt.
In
CHANNEL_CONTROL, RATIO, REF_ADDR1, REF_ADDR2, and REF_ADDR3 before issuing an HSR
%11. After each scheduled match event, an interrupt is issued to the host.
7
7.1
Like all TPU functions, OC function performance in an application is to some extent dependent upon the
service time (latency) of other active TPU channels. This is due to the operational nature of the scheduler.
The more TPU channels are active, the more performance decreases. However, worst-case latency in any
TPU application can be closely estimated. To analyze the performance of an application that appears to
approach the limits of the TPU, use the guidelines given in the TPU reference manual and the information
in the OC state timing table below.
MOTOROLA
1. 1. Writes parameters CHANNEL_CONTROL, REF_ADDR1, and other parameters, depending on
2. 2. Writes host sequence bit 1 according to mode of operation.
3. 3. Issues an HSR %01 for initiation of host-initiated pulse mode, or %11 for initialization of
4. 4. Enables channel servicing by assigning a high, middle, or low priority.
continuous
the mode of operation, to RAM.
continuous pulse mode. (The host-initiated pulse mode has no separate initialization state.
Initialization occurs each time the host-initiated pulse mode is executed.)
Function Configuration
Performance and Use of Function
Performance
pulse
mode,
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the
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CPU
configures
this
mode
by
providing
Performance
parameters
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