AN2372 Freescale Semiconductor / Motorola, AN2372 Datasheet - Page 8

• Manufacturer Part Number: AN2372
• Description: Using the Output Compare TPU Function (OC) with the MPC500Family
• Manufacturer: Freescale Semiconductor / Motorola

REF_ADDR2
4.5
REF_ADDR2 is also a pointer into the parameter RAM map. It is used only in continuous mode. It points
to a reference value that is scaled by the RATIO parameter to form a new OFFSET value whenever a link
is received.
4.6
REF_ADDR3 is a pointer into the parameter RAM map that points to a synchronization reference value
used only once in continuous pulse mode when the first link service request is serviced after initialization.
4.7
REF_TIME contains the TCR value when the next match event will occur, or the TCR value of the most
recent match event.
4.8
ACTUAL_MATCH_TIME contains the TCR value captured at the time of the last match event. This may
be used by the host CPU to estimate time available before the next match and to confirm that a change in
offset was effected as desired. The TBS field determines which TCR is captured and placed in this
parameter. This parameter is used only in the host-initiated pulse mode.
4.8.1
TCR1 and TCR2 are word locations 0xEC and 0xEE in the parameter RAM map. When
the HOST_MATCH state (S1) is executed, the most recent TCR1 value updates word location 0xEC, and
the most recent TCR2 value updates word location 0xEE.
5
This section provides information concerning the TPU host interface to the OC function. Table 3 is a TPU
address map. Detailed TPU register diagrams follow the table. In the diagrams, Y = M111, where M is the
value of the module mapping bit (MM) in the system integration module configuration register (Y = 0x7 or
0xF).
8
REF_ADDR2
REF_ADDR3
REF_TIME
ACTUAL_MATCH_TIME
Host Interface to Function
0x30YY0A
0x30YY0C
TCR1 and TCR2
0x30YY00
0x30YY02
0x30YY04
0x30YY06
0x30YY08
Address
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Using the Output Compare TPU Function
15
Table 3. TPU Address Map
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TPU Module Configuration Register (TPUMCR)
Development Support Control Register (DSCR)
Channel Function Section Register 0 (CFSR0)
Development Support Status Register (DSSR)
TPU Interrupt Configuration Register (TICR)
Channel Interrupt Enable Register (CIER)
Test Configuration Register (TCR)
8 7
MOTOROLA
0