CY2XP31 Cypress Semiconductor, CY2XP31 Datasheet - Page 6

• Manufacturer Part Number: CY2XP31
• Description: 312.5 MHz LVPECL Clock Generator
• Manufacturer: Cypress Semiconductor

Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices.
trates a typical filtering scheme. Because all of the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 9. Power Supply Filtering
Termination for LVPECL Output
The CY2XP31 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3 V
operation, this data sheet specifies output levels for termination
to V
for V
Note that it is also possible to terminate with 50 ohms to ground
(V
values. Termination resistors are best located close to the desti-
nation device. To avoid reflections, trace characteristic
impedance (Z
Figure 10
Document #: 001-06385 Rev. *H
SS
DD
(Pin 1)
DD
), but the high and low signal levels differ from the data sheet
(Pin 8)
V DD
V DD
–2.0 V. This same termination voltage can also be used
= 2.5 V operation, or it can be terminated to V
shows a standard termination scheme.
0
) should match the termination impedance.
0.1μF
0.01 µF
3.3V
10µ F
Figure 9
DD
-1.5 V.
illus-
Figure 10. LVPECL Output Termination
Crystal Input Interface
The CY2XP31 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
therefore layout dependent.
Figure 11. Crystal Input Interface
18 pF Parallel
Crystal
CLK#
CLK
X1
33 pF
27 pF
C1
C2
Z0 = 50Ω
Z0 = 50Ω
XOUT
XIN
Device
Figure 11
84Ω
125Ω
3.3V
84Ω
125Ω
CY2XP31
are deter-
Page 6 of 10
IN
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