AN2414 Freescale Semiconductor / Motorola, AN2414 Datasheet
AN2414
Related parts for AN2414
AN2414 Summary of contents
Page 1
... Freescale Semiconductor, Inc. Application Note AN2414/D Rev. 0, 04/2003 MC9328MX1/MXL CMOS Signal Interface (CSI) Module Supplementary Information By Cliff Wong 1 Introduction 1 Introduction . . . . . . . . . . 1 This document provides information on the architecture of the CSI module in addition to the 2 Operation of FIFOs Clear datasheet. Programmers should read about this before they write software drivers for sensors. ...
Page 2
Freescale Semiconductor, Inc. Operation of FIFOs Clear st 1 SOF FIFO clear takes place Write CLR_RXFIFO = ’1’ Write CLR_STATFIFO = ’1’ Write FCC = ’1’ MX1 v2.0 SYNC FIFO Clear is selected by setting FCC bit to ’1’. This ...
Page 3
Freescale Semiconductor, Inc. 2. Set CLR_STATFIFO to ’1’, then STAT FIFO is cleared immediately & kept at reset state. 3. When SOF arrives, STAT FIFO is released from reset state and starts working. 4. Set CLR_RXFIFO to ’1’, then RX ...
Page 4
Freescale Semiconductor, Inc. Sensor Interface Operation HSYNC is an active high signal that encapsulates valid pixel clocks. HSYNC & PIXCLK are passed through a logical-AND operation to generate valid pixel clocks. HSYNC & PIXCLK => Valid PIXCLK So, data is ...
Page 5
Freescale Semiconductor, Inc. 4 Sensor Interface Timing 4.1 Gated Clock Mode, Pixel Clock Rising-Edge Active VSYNC HSYNC PIXCLK DATA[7..0] Parameter PIXCLK Freq PIXCLK High Time PIXCLK Low Time Data Valid to PIXCLK High Tdpd (Setup Time) PIXCLK High to Data ...
Page 6
Freescale Semiconductor, Inc. Sensor Interface Timing 4.2 Gate-Clock Mode, Pixel Clock Falling-Edge Active VSYNC HSYNC PIXCLK DATA[7..0] Tphd Parameter PIXCLK Freq PIXCLK High Time PIXCLK Low Time Data Valid to PIXCLK Low Tdpd (Setup Time) PIXCLK Low to Data Invalid ...
Page 7
Freescale Semiconductor, Inc. 4.3 Non-Gated Clock Mode, Pixel Clock Rising-Edge Active VSYNC Tpvd PIXCLK DATA[7..0] Parameter PIXCLK Freq PIXCLK High Time PIXCLK Low Time Data Valid to PIXCLK High Tdpd (Setup Time) PIXCLK High to Data Invalid Tpdd (Hold Time) ...
Page 8
Freescale Semiconductor, Inc. Statistics 4.4 (4) Non-Gated Clock Mode, Pixel Clock Falling-Edge Active VSYNC Tpvd PIXCLK DATA[7..0] Parameter PIXCLK Freq PIXCLK High Time PIXCLK Low Time Data Valid to PIXCLK Low Tdpd (Setup Time) PIXCLK Low to Data Invalid Tpdd ...
Page 9
Freescale Semiconductor, Inc. 5.1 Live Veiw Resolution Mode (LVRM) The image is divided into square blocks, according to the choice made on the Live View Resolution Mode (LVRM). Statistic data is generated per each block. The output includes 4 16-bit ...
Page 10
Freescale Semiconductor, Inc. Statistics 5.3 Double Resolution Mode (DRM) Double Resolution Mode allows the vertical resolution of image to be enhanced, without increasing the complexity of hardware. User may find this useful when they fine tune the algorithm of white ...
Page 11
Freescale Semiconductor, Inc. MOTOROLA MC9328MX1/MXL Application Note For More Information On This Product, 16 column gap 640 pixels = ( Figure 11. Engineering Draft / Preliminary Go to: www.freescale.com Statistics 8 row gap 11 ...
Page 12
... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 AN2414/D Engineering Draft / Preliminary For More Information On This Product, Go to: www.freescale.com ...