AN2414 Freescale Semiconductor / Motorola, AN2414 Datasheet - Page 2

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AN2414

Manufacturer Part Number
AN2414
Description
CMOS Signal Interface (CSI) Module Supplementary Information for MC9328MX1 and MC9328MXL Application Note
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Operation of FIFOs Clear
MX1 v2.0
SYNC FIFO Clear is selected by setting FCC bit to ’1’. This bit only needs to be set in the init code. Once
it’s set, CLR_RXFIFO & CLR_STATFIFO bits are ignored. FIFO clear operation will take place
automatically on every SOF.
2.2 Asynchronous FIFO Clear
MX1 v1.0 & v2.0
There is no change from MX1 v1.0 to v2.0 for this part.
"ASYNC Clear" means that FIFOs are cleared immediately at the time when CLR_RXFIFO and
CLR_STATFIFO bits are set. For RXFIFO, it stars to work ASAP after reset. For STATFIFO, it is kept at
the reste state until next SOF arrives.
Proper usage should be :
2
1. In the int code, clear FCC bit to ’0’ to select ASYNC clear mode.
Write FCC = ’1’
Write FCC = ’1’
1
1
Write CLR_RXFIFO = ’1’
Write CLR_STATFIFO = ’1’
st
st
Freescale Semiconductor, Inc.
SOF
SOF
For More Information On This Product,
FIFO clear takes place
FIFO clear takes place
MC9328MX1/MXL Application Note
FIFO starts working
FIFO starts working
Engineering Draft / Preliminary
Go to: www.freescale.com
Figure 1.
Figure 2.
2
Write CLR_RXFIFO = ’1’
Write CLR_STATFIFO = ’1’
2
nd
nd
SOF
SOF
FIFO clear takes place
FIFO clear takes place
FIFO starts working
FIFO starts working
MOTOROLA

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