AN2654 Freescale Semiconductor / Motorola, AN2654 Datasheet - Page 3

• Manufacturer Part Number: AN2654
• Description: Interfacing SDRAM Devices to the MPC8280 at 100 MHz
• Manufacturer: Freescale Semiconductor / Motorola

1
Activating the data pipeline mode by setting BRx[DR] in the memory controller improves the AC timing
because data beat accesses to memory controller address spaces are delayed by one cycle.With this mode
enabled the output timing for the data bus and DP pins are the same as the timing for a normal bus.
MOTOROLA
1
Spec Number
Spec Number
Setup Hold
sp33a
sp33b
sp35a
sp11a
sp13a
sp14a
sp31
sp32
sp34
sp35
sp11
sp12
sp13
sp14
sp15
Max
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
sp30 PSDVAL/TEA/TA
sp30 ADD/ADD_atr/BADDR/CI/GBL/WT
sp30 Data bus
sp30 DP
sp30 Memory controller signals/ALE
sp30 All other signals
sp30 AP
sp10 AACK/TA/TS/DBG/BG/BR
sp10 ARTRY/ TEA
sp10 Data bus in normal mode
sp10 Data bus in ECC and PARITY modes
sp10 Pipeline mode—Data bus in ECC and PARITY modes
sp10 DP pins
sp10 Pipeline mode—DP pins
sp10 All other pins
Min
Interfacing SDRAM Devices to the MPC8280 at 100 MHz
Freescale Semiconductor, Inc.
Table 2. AC Characteristics for SIU Outputs
Table 1. AC Characteristics for SIU Inputs
For More Information On This Product,
Go to: www.freescale.com
Characteristic
Characteristic
Bus Interface Timing Specifications
1
1
Maximum
100 MHz
100 MHz
Setup
Delay
3.5
3.5
3.5
2.5
3.5
2.5
3.5
5.5
5.5
5.5
5.5
5.5
5.5
4
7
Value (ns)
Value (ns)
Minimum
100 MHz
100 MHz
Delay
Hold
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.7
1
1
1
1
1
1
3