AN2654 Freescale Semiconductor / Motorola, AN2654 Datasheet - Page 5

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AN2654

Manufacturer Part Number
AN2654
Description
Interfacing SDRAM Devices to the MPC8280 at 100 MHz
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
If, in a system with a clock driver with a 0.1-ns skew between the SDRAM clock and the MPC8280 clock,
we assume an equal track length between the clock driver and the MPC8280 and the clock driver and the
SDRAM, there is still a margin of 0.1 ns in the interface. Also, the longer tracks between the MPC8280 and
the SDRAM add more margin to both the read and write cycles.
For further information on implementing clock skew and track delay into a design, please refer to the
“Timing Considerations when Interfacing PQII to SDRAM” white paper that is detailed in Section 4,
“Reference Material.”
4 Reference Material
The documents listed in Table 3 are all available at http://www.motorola.com/semiconductors/:
5 Conclusion
The above analysis has shown that with careful design practice the MPC8280 will have a glueless interface
to standard SDRAM memory devices while operating at bus frequencies up to and including 100 MHz.
MOTOROLA
MPC8260 PowerQUICC II™ Family Reference Manual
MPC8280 Addendum to the MPC8260 PowerQUICC II Family Reference Manual
“MPC8280 PowerQUICC II Family Device Errata”
“MPC8280 Family Hardware Specifications”
“MPC8260 PowerQUICC II Design Checklist”
“MPC8260 SDRAM Timing Diagram”
“Timing Considerations when Interfacing the PowerQUICC II to SDRAM”
Interfacing SDRAM Devices to the MPC8280 at 100 MHz
Freescale Semiconductor, Inc.
For More Information On This Product,
Title
Go to: www.freescale.com
Table 3.
MPC8260UM
MPC8280UMAD
MPC8280CE
MPC8280EC
AN2290
AN2178
MPC826XSDRAMWP
Document Order Number
Reference Material
5

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