AN2654 Freescale Semiconductor / Motorola, AN2654 Datasheet - Page 4

• Manufacturer Part Number: AN2654
• Description: Interfacing SDRAM Devices to the MPC8280 at 100 MHz
• Manufacturer: Freescale Semiconductor / Motorola

Interface to SDRAM at 100 MHz
Interface to SDRAM at 100 MHz
3 Interface to SDRAM at 100 MHz
The on-chip SDRAM controller on the MPC8280 is designed to provide a ‘glueless’ interface to standard
SDRAM devices and DIMM modules. The electrical specification for standard SDRAM devices defines the
following timing:
3.1 MPC8280 Writing to SDRAM
At a bus frequency of 100 MHz the cycle time is 10 ns. When the MPC8280 writes to the SDRAM the
address and address attributes are valid at a maximum 5.5 ns (sp32/sp30) after a rising clock edge. The
SDRAM requires a minimum 1.5 ns of setup time before the next rising edge.
Therefore, this allows 10 – 5.5 – 1.5 = 3 ns for clock skew and track delay in the interface. The MPC8280
outputs the data also at a maximum of 5.5 ns (sp33a/sp30) after a rising clock edge and the SDRAM requires
only a minimum setup time of 1.5 ns for data.
This allows 10 – 5.5 – 1.5 = 3 ns for clock skew and track delay. The MPC8280 maintains the data for 0.7 ns
after the clock edge or for 1 ns after the clock edge if the load is greater than 20 pF. The SDRAM device
requires a hold time of 0.8 ns. Therefore, there is a margin of 0.2 ns because the control signals from the
MPC8280 are held for 1 ns and the SDRAM device only requires 0.8 ns.
3.2 MPC8280 Reading from SDRAM
During a read cycle from the MPC8280 to the SDRAM the address and address attributes are valid at a
maximum of 5.5 ns (sp32/sp30) after a rising clock edge. The SDRAM requires a minimum of 1.5 ns of
setup time before the next rising edge. This again allows 10 – 5.5 – 1.5 = 3 ns for clock skew and track delay.
The SDRAM outputs the required data at a maximum of 5.4 ns after the rising clock edge for a PC133
SDRAM with a CAS latency of 3. The MPC8280 requires 3.5 ns (sp12/sp10) for setup time. This leaves
10 – 5.4 – 3.5 = 1.1 ns for clock skew and track delay.
The SDRAM maintains the data for 3 ns for normal load but only 1.8 ns for low loads. The MPC8280
requires a hold time of only 0.5 ns. Therefore, even with a low load there is a margin of 1.8 – 0.5 = 1.3 ns.
Again, the control signals from the MPC8280 are held for 1 ns and the SDRAM device requires only 0.8 ns.
Therefore there is a margin of 0.2 ns for track delay and clock skew.
3.3 Restriction on the Interface to SDRAM
The above timing analysis shows that for an ideal situation with zero clock skew between the MPC8280 and
the SDRAM the timing requirements are all met. The 0.2-ns margin is small but, assuming a PCB track
delay of approximately 0.1 ns per inch, the margin allows for track lengths of up to 2 inches (5 cm).
In a real design there will be clock skew present between the MPC8280 and the SDRAM that will negatively
affect the margins. However, there will also be longer track lengths that will have a positive effect by
increasing the signal delay.
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Inputs
— Setup time for ADDRESS, DATA, CS, RAS, CAS, WE, DQM is 1.5 ns minimum
— Hold time for all signals is 0.8 ns
Outputs
— Data output hold time is a minimum of 3 ns for normal loads and 1.8 ns for a low load situation
Interfacing SDRAM Devices to the MPC8280 at 100 MHz
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA