AN2826 Freescale Semiconductor / Motorola, AN2826 Datasheet - Page 4

• Manufacturer Part Number: AN2826
• Description: DDR-SDRAM Layout Considerations for MCF547x/8x Processors
• Manufacturer: Freescale Semiconductor / Motorola

DDR SDRAM Overview
resistors, both series (22 ohm) and parallel (51 ohm), to most of the DDR SDRAM signals between the
MPU and the DDR SDRAM. On the validation board these termination resistors are housed in resistor
packs to save PCB space.
2.1
The MCF547x/8x SDRAM controller contains a glueless interface to both SDR and DDR SDRAMs.
Systems can contain either SDR SDRAM or DDR SDRAM, but a system containing both forms of
SDRAM is not supported. The memory port width is fixed at 32 bits. Once data arrives on-chip there is a
64-bit data bus interface to the internal XLB 64-bit bus; this avoids any bandwidth bottlenecks on the
SDRAM interface. The SDRAM controller also supports 32-byte critical word first burst transfers to aid
with cache line fills. In terms of SDRAM device internal configurations supported, the controller can
support up to 13 row address lines, up to 12 column address lines, 2 bits of bank address, and a maximum
of four SDRAM chip selects. The maximum row bits plus column bits can be less than or equal to 24.
Given current SDRAM memory devices, this enables support for up to 1 Gbyte of memory to be accessed:
either 13+11 or 12+12 bits of, respectively, RA (Row Address) + CA (Column Address), 2-bit BA (Bank
Address), and four chip selects (CS). The minimum memory configuration supported is 8 Mbytes: an
11-bit RA, 8-bit CA, 2-bit BA and one chip select. The SDRAM controller also supports page mode to
maximize the data rate, SDRAM sleep mode, and self-refresh mode. Please note, error detection and parity
checking are not supported by this SDRAM controller.
As stated the SDRAM controller supports up to 13 row addresses and up to 12 column addresses. When
the SDRAM controller receives the internal module enable signal, it latches the internal bus address lines
addresses[27:2] and multiplexes them into row, column, and row bank addresses. Addresses[9:2] are
always used for CA[7:0], addresses[11:10] are always used for BA[1:0], and addresses[23:12] are always
used for RA[11:0]. Addresses[27:24] can be used for additional row or column address bits, as needed.
Table 1
4
shows the address multiplexing schemes available for this SDRAM controller.
DDR SDRAM Controller Implemented on the
MCF547x/8x Family
The SDRAM controller only supports an external 32-bit data bus. It is not
possible to connect a smaller device(s) to only part of the SDRAM’s data
bus. For example, if 16-bit wide devices are used, then two 16-bit devices
must be connected as a 32-bit port.
DDR-SDRAM Layout Considerations for MCF547x/8x Processors, Rev. 1
NOTE
Freescale Semiconductor