EM6A9320 Etron Technology Inc., EM6A9320 Datasheet - Page 7

• Manufacturer Part Number: EM6A9320
• Description: 4M x 32 DDR SDRAM
• Manufacturer: Etron Technology Inc.

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Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and WE#.
The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS#, RAS#,
CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to
writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or
matched impedance. Two clock cycles are required to complete the write operation in the extended mode
register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is
used for EMRS. Refer to the table for specific codes.
Extended Mode Resistor Bitmap
Power up Sequence
Etron Confidential
BA0 Mode
BA1
0
1
0
1) Apply power to V
2) Start clock and maintain stable condition for minimum 200us.
3) Issue a “NOP” command and keep CKE “HIGH”
4) Issue a “Precharge All” command.
5) Issue EMRS – enable DLL.
6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS – with A8 to low to initialize the mode register.
Power up must be performed in the following sequence.
EMRS
MRS
"NOP" state and maintain CKE “LOW”.
BA0
1
A6 A1
A11
0
0
1
1
0
1
0
1 Matched impedance
RFU must be set to “0”
DD
A10
Drive Strength
SSTL-2 weak
before or at the same time as V
RFU
Full
A9
A8
Strength
4Mx32 DDR SDRAM
100%
RFU
60%
30%
A7
7
Do not use
Output driver matches impedance
DS1
A6
DDQ,
Comment
V
A5
TT
RFU must be set to “0”
and V
A4
REF
when all input signals are held
A3
Rev 0.3
EM6A9320
A2
DS0
A1
A0
0
1
July. 2002
Disable
Enable
DLL
DLL
A0