SSD1325 Solomon Systech, SSD1325 Datasheet - Page 13

• Manufacturer Part Number: SSD1325
• Description: OLED/PLED Driver
• Manufacturer: Solomon Systech

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FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder
This module determines whether the input data is interpreted as data or command. Data is interpreted
based upon the input of the D/C# pin.
If D/C# pin is high, the input at D
input at D
command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
R/W#(WR#) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the
status register. R/W# (WR#) input Low indicates a write operation to Display Data RAM or Internal
Command Registers depending on the status of D/C# input. The E (RD#) input serves as data latch
signal (clock) when high provided that CS# is low. Refer to Parallel Interface Timing Diagram of 6800-
series microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 3 below.
MPU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D
E (RD#) input serves as data read latch signal (clock) when it is low, and provided that CS# is low. Data
read latch signal is disable when E (RD#) is high. Display data or status register read is controlled by
D/C#. R/W# (WR#) input serves as data write latch signal (clock) when it is low and provided that CS# is
low. Display data or command register write is controlled by D/C#. Refer to Parallel Interface Timing
Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required
before the first actual display data read.
MPU Serial Interface
The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. SDIN is shifted into an 8-
bit shift register on every rising edge of SCLK in the order of D
eighth clock and the data byte in the shift register is written to the Display Data RAM or command register
in the same clock.
SSD1325
R/W#(WR#)
E(RD#)
7
-D
Data
0
is interpreted as a Command which will be decoded and be written to the corresponding
Figure 3 - Display Data Read Back Procedure - Insertion of Dummy Read
Rev 1.2
Write address
P 13/53 Aug 2005
N
7
-D
0
is written to Graphic Display Data RAM (GDDRAM). If it is low, the
Dummy read
Data read1
n
7
-D
7
0
-D
), E (RD#), R/W#(WR#), D/C#, CS#. The
7
, D
0
), R/W#(WR#), D/C#, E (RD#), CS#.
6
, ... D
n+1
Data read2
0
. D/C# is sampled on every
Data read3
n+2
Solomon Systech