MTD508 Myson Technology, MTD508 Datasheet
MTD508
Related parts for MTD508
MTD508 Summary of contents
Page 1
... Ethernet switch device. The MTD508 supports 8 RMII ports for 10M/100M operations. 1MBytes/2MBytes memory interface provides maximum 1365 packet buffers for Ethernet packet buffering 8192 address entries are provided by the MTD508, and the MTD508 uses full Ethernet address to minimizing hashing collision events. ...
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... Myson-Century Technology www.DataSheet4U.com SYSTEM DIAGRAM SGRAM (256k32x1) SGRAM (512k32x1) SDRAM (256k32x2) (**Optional) (**Programmable) EEPROM MTD508 RMII0-3 QUAD PHYsceiver MII management QUAD Transformer RJ45 MTD508 LEDs RMII4-7 QUAD PHYsceiver QUAD Transformer RJ45 page ...
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... GNDI 151 VCCI 152 RXD0_0 153 RXD0_1 154 CRSDV1 155 TXD1_1 156 TXD1_0 157 TXEN1 158 RXD1_0 159 RXD1_1 160 MTD508 160-pin PQFP MTD508 VCCO 80 GNDO 79 78 AD5 AD6 77 76 AD7 AD8 75 74 VCCI 73 MEMCLK GNDI 72 71 DO8 DQ9 70 69 ...
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... Port MII receive data bit3. In RMII mode, this pin is not used. 29 Port MII receive data bit2. In RMII mode, this pin is not used. 27 Port MII receive data bit0. 28 Port MII receive data bit1. 21 Port4 RMII transmit enable signal. MTD508 Description page ...
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... Port7 RMII transmit data bit1. SGRAM/SDRAM Interface Pins Pin 75-78, 81-82, Memory row/column address bus outputs. 85-87 AD[7:0] are row/column address[7:0]. AD[8]: This pin should connect to SGRAM/SDRAM MSB address bit. 54-58, 61-71, Memory data bus. 96-98, 101, 104-107, 110- 115, 118-119 93 SGRAM/SDRAM row address select. MTD508 Description Description page ...
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... MII management data inout. 135 MII register clock inout. 136 MII register data inout. 138 EEPROM data input. 137 EEPROM clock output. Description Description [1] [2] [3] [4] [5] LR1 LR2 LR3 LR4 - Uti1 Uti2 Uti3 Uti4 - Description MTD508 [6] [ BFull MFail page ...
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... The default value is “1”. During power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). EEDATA: enable EEPROM auto-load configuration function while EEPROM interface is enabled, 1: enable; 0: disable. The default value is “1”. MTD508 Description Description page ...
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... The default value is “0”. During power on reset duration, this pin is a jumper setting pin (pull_high = 1, pull_low = 0). MDC: fast mode enable, 1: fast mode enable; 0: fast mode disable. the default value is “0”. MTD508 Description page ...
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... FUNCTIONAL DESCRIPTION The MTD508 is an 8-port 10/100Mbps fast Ethernet switch controller low-cost solution for eight ports fast Ethernet SOHO switch design. No CPU interface is required. After power on reset, the MTD508 provides an auto load configuration setting function through a 2-wire serial EEPROM interface to access external EEPROM device, and the MTD508 can easily be configured to support port-trunking, port-VLAN, static entry, 802.3x flow control threshold setting, flooding port assignment... etc. functions. The following descriptions are the MTD508’ ...
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... Xon_TH value), the MTD508 will send a JAM pattern in the input port when it senses an incoming packet, thus forcing a collision to inform the remote node transmission back off and will effectively avoid dropping packets. If the “back pressure control enable” ...
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... Port Based VLAN The MTD508 supports VLAN configuration by port based methodology. One port selects the certain ports to form its VLAN group by configuring the VLAN register. The packet (including broadcast packet) is not forwarded to the destination port whose VLAN group is different from the source port. ...
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... LEDCLK1 rising edge and LEDDATA[7:0] are used to report Port7-0 link/receive activity led status. LEDCLK2 rising edge and LEDDATA[4:0] are used to report packet buffer utilization rating, and LEDDATA[7] is used to report external memory test result (after power reset, the MTD508 will test external SDRAM automatically), and LEDDATA[6] reports the buffer almost full alarm signal. ...
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... Myson-Century Technology www.DataSheet4U.com INTERNAL MII REGISTERS The MTD508 implements 10 MII global registers and 4-per-dot registers, defined as the following tables: Table 1. MII Registers Reg No. Bit Name 0 CtlReg0 8-0 12-9 15-13 1 CtlReg1 7-0 XON 15-8 XOFF 2 CtlReg2 15-0 Aging 3 CtlReg3 15-0 Uplink Reg0 4 CtlReg4 15-0 Uplink Reg1 5 CtlReg5 7-0 8 15-9 6 StsReg0 Global Registers ...
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... Port Registers R/W Description RO Status Register 1 bit[10:0]: output Port Tx queue head value. Reserved. RO Status Register 2 bit[10:0]: output Port Tx queue tail value. Reserved. RO Status Register 3 bit[10:0]: output Port Tx queue count value. Reserved. R/W bit[7:0]: select Port VLAN group. Reserved. MTD508 Default Default page ...
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... I Resistance (Under recommended operating conditions and VCC = 3.0 ~ 3.6V 115 C) Parameter Parameter Conditions no pull-up or down CMOS CMOS 12, 16, 24mA 12, 16, 24mA MTD508 Rating -0.3 to 3.6 -0 0 0.3 CC -55 to 150 Min Typ Max 3.0 3.3 3 ...
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... MII input setup time T6 MII input hold time T7 MII output setup time T8 MII output hold time T1 Valid T3 Valid Figure-1 RMII Timing Parameter T5 Valid T7 Valid Figure-2 MII Timing Parameter MTD508 T2 T4 Min Typ Max Min Typ Max Unit ...
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... Row active to burst write MEMCLK RASB CASB WEB AD[8:0] DQ[31: Figure-3 Memory Write Timing Parameter Valid Valid Figure-4 Memory Read Timing MTD508 Valid T7 T6 Valid Min Typ Max T10 Valid Unit CLK page ...
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... EEPROM clock cycle T15 EEDDATA input setup time T16 EEDATA input hold time Parameter T12 Valid Figure-5 EEPROM Timing Parameter T14 T15 T16 Valid Valid Figure-6 LED Interface Parameter MTD508 Min Typ Max 2 2 T11 T13 Min Typ Max Valid Min Typ ...
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... Dimensions in Inches Min Nom Max - - 0.145 0.006 - - 0.107 0.112 0.117 0.007 0.009 0.011 0.004 - 0.008 0.906 0.913 0.921 0.783 0.787 0.791 0.669 0.677 0.685 0.547 0.551 0.555 0.020BCS 0.029 0.035 0.041 0.063BCS - - 0.004 MTD508 page ...