MTD508 Myson Technology, MTD508 Datasheet - Page 5

• Manufacturer Part Number: MTD508
• Description: 8-port Switch
• Manufacturer: Myson Technology

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TXCLK4
TXD4_3
TXD4_2
TXD4_0
TXD4_1
COL4
CLK25M
CRSDV5
RXD5_0
RXD5_1
TXEN5
TXD5_0
TXD5_1
CRSDV6
RXD6_0
RXD6_1
TXEN6
TXD6_0
TXD6_1
CRSDV7
RXD7_0
RXD7_1
TXEN7
TXD7_0
TXD7_1
AD[8:0]
DQ[31:0]
RASB
Name
Name
Myson-Century Technology
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
104-107, 110-
75-78, 81-82,
54-58, 61-71,
115, 118-119
96-98, 101,
85-87
155
Pin
Pin
22
17
18
20
19
16
31
35
36
34
33
32
37
41
42
40
39
38
43
39
50
46
45
44
93
SGRAM/SDRAM Interface Pins
Port4 RMII transmit clock signal. In RMII mode, this pin is not used.
Port4 MII transmit data bit3. In RMII mode, this pin is not used.
Port4 MII transmit data bit2. In RMII mode, this pin is not used.
Port4 RMII/MII transmit data bit0.
Port4 RMII/MII transmit data bit1.
Port4 MII collision input. In RMII mode, this pin is not used.
Port4 MII 25MHz clock output.
Port5 RMII receive interface signal, CRSDV5 is asserted high when port5
media is non-idle.
Port5 RMII receive data bit0.
Port5 RMII received data bit1.
Port5 RMII transmit enable signal.
Port5 RMII transmit data bit0.
Port5 RMII transmit data bit1.
Port6 RMII receive interface signal, CRSDV6 is asserted high when port5
media is non-idle.
Port6 RMII receive data bit0.
Port6 RMII received data bit1.
Port6 RMII transmit enable signal.
Port6 RMII transmit data bit0.
Port6 RMII transmit data bit1.
Port7 RMII receive interface signal, CRSDV7 is asserted high when port5
media is non-idle.
Port7 RMII receive data bit0.
Port7 RMII received data bit1.
Port7 RMII transmit enable signal.
Port7 RMII transmit data bit0.
Port7 RMII transmit data bit1.
Memory row/column address bus outputs.
AD[7:0] are row/column address[7:0].
AD[8]: This pin should connect to SGRAM/SDRAM MSB address bit.
Memory data bus.
SGRAM/SDRAM row address select.
RMII/MII Port Interface Pins
Description
Description
MTD508
page 5 of 19