AD8197B Analog Devices, AD8197B Datasheet - Page 16

• Manufacturer Part Number: AD8197B
• Description: 4:1 HDMI/DVI Switch with Equalization
• Manufacturer: Analog Devices

AD8197B
GENERAL CASE
READ PROCEDURE
To read data from the AD8197B register set, an I
(such as a microcontroller) needs to send the appropriate
control signals to the AD8197B slave device. The signals are
controlled by the I
diagram of the procedure, see Figure 30. The steps for a read
procedure are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for the AD8197B to acknowledge the request.
11. The AD8197B serially transfers the data (eight bits) held in
12. Acknowledge the data from the AD8197B.
Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
Send the AD8197B part address (seven bits). The upper
four bits of the AD8197B part address are the static value
[1001] and the three LSBs are set by Input Pin
I2C_ADDR2, Input Pin I2C_ADDR1, and Input Pin
I2C_ADDR0 (LSB). This transfer should be MSB first.
Send the write indicator bit (0).
Wait for the AD8197B to acknowledge the request.
Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first.
Wait for the AD8197B to acknowledge the request.
Send a repeated start condition (Sr) by holding the
I2C_SCL line high and pulling the I2C_SDA line low.
The upper four bits of the AD8197B part address are the
static value [1001] and the three LSBs are set by the Input
Pin I2C_ADDR2, I2C_ADDR1 and Input Pin I2C_ADDR0
(LSB). This transfer should be MSB first.
Send the read indicator bit (1).
the register indicated by the address set in Step 5. This data
is sent MSB first.
EXAMPLE
Resend the AD8197B part address (seven bits) from Step 2.
I2C_SDA
I2C_SDA
I2C_SCL
START
1
2
C master, unless otherwise specified. For a
FIXED PART
2
ADDR
ADDR
R/W
3
ACK
4
5
2
C master
REGISTER ADDR
Figure 30. I
Rev. 0 | Page 16 of 28
2
C Read Diagram
ACK
6
7
SR
13. Perform one of the following:
SWITCH
There is a delay between when a user
tion registers of the AD8197B and when that state change take
physical effect. This update delay occurs regardless of whether
the user programs the AD8197B via the serial or the parallel
control interface. When using the serial control interface, the
update delay begins at the falling edge of I2C_SCL for the last
data bit transferred, as shown in Figure 29. When using the
parallel control interface, the update delay begins at the transi
edge of the relevant parallel interface pin. This update delay is
register-specific and the times are specified in Table 1.
During a delay window, new values can be written to the
configuration registers, but the AD8197B does not physica
update until the end of that register’s delay window. Writing
new values during the delay window does not reset the windo
new values supersede the previously written values. At the end
of the delay window, the AD8197B physically assumes the state
indicated by the last set of values written to the configuration
registers. If the configuration registers are written after the dela
window ends, the AD8197B immediately updates and a new
delay window begins.
FIXED PART
13a. S
13b.
13c.
13d.
8
ADDR
line high, pull the SDA line high) and release control
of the bus to end the transaction (shown in
Send a repea
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the write procedure (previous
Write Procedure section) to perform a write.
Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of this procedure to perform a
read from another address.
Send a repeated start conditi
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of this procedure to perform a
read from the same address.
ING/UPDATE DELAY
end a st
ADDR
op condition (while holding the I2C_SCL
ted start condition (while holding the
R/W
9 10 11
ACK
writes to the configura-
on (while holding the
DATA
ACK
12
Figure 30
STOP
13
lly
tion
w;
s
).
y