SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 57

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

7.5
SPC8104
Symbol
t14
t10
t11
t12
t13
412-1.0
t1
t2
t3
t4
t5
t6
t7
t8
t9
SPC8104 outputs
MA[9:0]
RAS#
LCAS#
UCAS#
DRAM outputs
MD[15:0]
DRAM Read Cycle Timing - Page Mode
MA[9:0] row address setup to RAS# asserted
MA[9:0] row address hold from RAS# asserted
RAS# precharge
RAS# pulse width
RAS# asserted to LCAS#, UCAS# asserted
MA[9:0] col. address setup to LCAS#, UCAS# asserted(1st)
MA[9:0] col. address hold from LCAS#, UCAS#
asserted(1st)
LCAS#, UCAS# asserted to RAS# negated
LCAS#, UCAS# pulse width
MD[15:0] read data setup to LCAS#, UCAS# negated
MD[15:0] read data hold from LCAS#, UCAS# negated
MA[9:0] column address setup to LCAS#, UCAS# asserted
(2
MA[9:0] column address hold from LCAS#, UCAS#
asserted
(2
LCAS#, UCAS# precharge
nd
nd
-n
-n
th
th
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
page access)
page access)
t3
Figure 8 : DRAM Read Cycle Timing - Page
t1
row
t2
Table 0-23 DRAM Read Cycle Timing - Page Mode
t5
t6
Parameter
column 1
t9
t10
t7
valid
t11
t14
X15-SP-001-08.1
t12
column 2
t4
t9
t10
t13
valid
ModeSource: a000074.cdr
t11
0.5Ts-2
3.5Ts-5
1.5Ts-5
0.5Ts-2
0.5Ts-2
0.5Ts-8
2Ts-12
Ts-15
Ts-13
Ts-20
0.5Ts
(n=2)
Ts-5
Min
10
0
Hardware Functional Specification
Typ
column
t8
t9
t10
6.5Ts-5
valid
(n=4)
Max
t11
Units
SP1-31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns