SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 90

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SPC8104

Manufacturer Part Number
SPC8104
Description
VGA LCD CONTROLLER
Manufacturer
S-MOS Systems
Datasheet

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bits 7-5
bit 0
bits 7-0
bits 7-0
bits 3-0
Hardware Functional Specification
08 Primary Revision Code Register RO
bit 2
09 Frame Buffer End High Register RW
bit 15
0A Frame Buffer End Low Register RW
bit 7
0C Configuration Readback Register RO
n/a
SP1-64
S-MOS Systems, Inc. • Tel: (408) 922-0200 • Fax: (408) 922-0238 • http://www.smos.com
Primary Revision Code
n/a
bit 1
bit 14
bit 6
Primary Revision Code Bits [2:0]
The Primary Revision Code Bits 2 to 0 are read-only bits permanently set to 1. The current revision
code of the chip is a combination of the primary and secondary revision code values. The second-
ary revision code bits are contained in register 0Fh.
Starting Address Bit 16
This bit is used to set the most significant display start address bit when utilizing the upper 256K
bytes of display memory to provide the Extended Display Page function. Along with the lower 16
bits of start address in CRTC registers 0Ch and 0Dh, this bit allows setting the start address of the
image displayed to be anywhere in the 256K address space. For this bit to have an effect, the
Extended Display Page enable bit (AUX[05] bit 0) must be set to 1.
Frame Buffer End Position Bits [15:8]
These are the 8 most significant bits of the a 16-bit total which determines the end address of the
frame buffer. For a given panel size of Width x Height and a given 18-bit frame buffer start address,
the 16-bit frame buffer end address is given by the following formula:
End Address = Lower 16 bit of {Start Address + (Height/2) [(Width -1) DIV 16 + 1] - 2}
Frame Buffer End Position Bits [7:0]
These are the 8 least significant bits of the a 16-bit total which determines the end address of the
frame buffer.
MD[3:0] Status on Reset
These are read-only bits which may be used for inputting power-up reset information to be read by
software. On the falling edge of the RESET input, the logic values on the MD[3:0] pins are latched
into the chip and then may be read in this register. These bits have no effect in hardware. Internal
pullups on these input pins ensure that if nothing is connected externally to these inputs, then
these register bits will read 1111.
n/a
bit 0
bit 13
bit 5
Frame Buffer End Position High Byte
Frame Buffer End Position Low Byte
n/a
n/a
bit 12
bit 4
X15-SP-001-08.1
MD3 Status
on Reset
RO
n/a
bit 11
bit 3
MD2 Status
on Reset
RO
n/a
bit 10
bit 2
MD1 Status
on Reset
RO
n/a
bit 9
bit 1
Starting
Addr. bit 16
bit 8
bit 0
MD0 Status
on Reset
RO
412-1.0
SPC8104

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