SPCE061A Sunplus Technology Co., Ltd., SPCE061A Datasheet - Page 8

• Manufacturer Part Number: SPCE061A
• Description: 16-bit sound controller with 32k x 16 flash memory
• Manufacturer: Sunplus Technology Co., Ltd.

5.5. Low Voltage Detection and Low Voltage Reset
5.5.1. Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) reports the circumstance of
present voltage. There are four LVD levels to be selected: 2.4V,
2.8V, and 3.2V.
Port_LVD_Ctrl (W).
2.8V.
Port_LVD_Ctrl is read as HIGH. In such state, program can be
designed to react to this condition.
5.5.2. Low voltage reset
In addition to the LVD, the SPCE061A has another important
function, Low Voltage Reset (LVR).
reset signal is generated to reset system when the operating
voltage drops below 2.2V for 4 consecutive clock cycles. Without
LVR, the CPU becomes unstable and malfunction when the
operating voltage drops below 2.2V.
functions to the initial operational (stable) states when the voltage
drops below 2.2V. A LVR timing diagram is given as follows:
5.6. Interrupt
The SPCE061A has 14 interrupt sources, grouped into two types,
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt
while IRQ is the low-priority one. An IRQ can be interrupted by a
FIQ, but not by another IRQ. A FIQ cannot be interrupted by any
other interrupt sources.
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Proprietary & Confidential
RESET
Fosc
VDD
2.2V
When the voltage drops below 2.8V, the b15 of
Tw=Fosc x 4 cycle
Tvdd > Tw
Treset = Fosc x512 cycle
These levels can be programmed via
As an example, suppose LVD is given to
Tvdd
Tw
With the LVR function, a
The LVR will reset all
Treset
8
5.7. I/O
Two I/O ports are built in SPCE061A, PortA and PortB.
PortA is an ordinary I/O with programmable wakeup capability. In
addition to the regular IO function, the PortB can also perform
some special functions in certain pins.
voltage is running at 3.6V (VDD) and VDDIO (power for I/O)
operates from 3.6V (VDD) to 5.5V. In such condition, the I/O pad
is capable of operating from 0V through VDDIO. The following
diagram is an I/O schematic.
Although data can be written into the same register through
Port_Data and Port_Buffer, they can be read from different places,
Buffer (R) and Data (R). The IOA [7:0] is the key wakeup port.
To activate key wakeup function, latch data on PORT_IOA_Latch
and enable the key wakeup function. Wakeup is triggered when
the PortA state is different from at the time latched. In addition to
an ordinary I/O port, PortB carries some special functions.
summary of PortB special functions is listed as follows:
UART (TxRDY or RxRDY)
Key change wakeup
Port_ATTR(R/W)
Interrupt Source
Port_Buffer(W)
Port_DIR(R/W)
Port_Data(W)
Time-base 1
Time-base 2
Fosc/1024
Timer A
Timer B
4096Hz
2048Hz
1024Hz
EXT2
EXT1
4Hz
2Hz
Buffer(R)
Data(R)
Control
Register
logic
FIQ_PWM/IRQ0_PWM High(FIQ)
FIQ_TMA/ IRQ1_TMA
FIQ_TMB/ IRQ2_TMB
Interrupt Name
IRQ4_2KHZ
IRQ6_TMB1
IRQ6_TMB2
IRQ3_EXT2
IRQ3_EXT1
IRQ4_4KHz
IRQ4_1KHz
IRQ3_KEY
UART IRQ
IRQ5_4Hz
IRQ5_2Hz
SPCE061A
Preliminary Version: 0.1
P
P
pull high
pull low
Suppose operating
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AUG. 02, 2002
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High(FIQ)
High(FIQ)
Pin pad
Priority
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Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
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