VG36128161BT-8H Powerchip, VG36128161BT-8H Datasheet - Page 18

• Manufacturer Part Number: VG36128161BT-8H
• Description: CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

7. Precharge
idle state after t
t
clocks can be calculated by dividing t
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
VIS
DPL(min.)
Document :1G5-0183
PrechargeE
The precharge command can be asserted anytime after t
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
In order to write all data to the memory cell correctly, the asynchronous parameter ”t
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
CAS latency = 2
CLK
Command
DQ
Command
CAS latency = 3
DQ
specification defines the earliest time that a precharge command can be asserted. The minimum number of
RP(min.)
is satisfied. The parameter t
CAS latency
2
3
T0
DPL(min.)
Read
Read
T1
with the clock cycle time.
RP
is the time required to perform the precharge.
Read
-1
-2
T2
RAS(min.)
Rev.5
Q0
VG36128401B / VG36128801B / VG36128161B
is satisfied.
T3
Q0
+ t
+ t
Q1
DPL(min.)
DPL(min.)
Write
CMOS Synchronous Dynamic RAM
T4
Q1
PRE
PRE
Q2
T5
Q2
Q3
DPL
” must be satisfied. The
T6
(t
Page 18
Q3
RAS
Hi - Z
is satisfied)
T7
Burst lengh=4
Hi - Z