VG36128161BT-8H Powerchip, VG36128161BT-8H Datasheet - Page 26

• Manufacturer Part Number: VG36128161BT-8H
• Description: CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

10.2.2 Precharge Termination in WRITE Cycle
invalid data in.
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
VIS
command
Document :1G5-0183
DQM
DQ
CAS latency = 3
CAS latency = 2
DQM
CLK
Command
DQ
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However,
T0
Write
Write
D0
D0
T1
D1
D1
T2
RP
D2
D2
from the precharge command. The DQM must be high to mask
T3
Rev.5
D3
D3
VG36128401B / VG36128801B / VG36128161B
T4
PRE
PRE
D4
D4
T5
CMOS Synchronous Dynamic RAM
t
RP
Hi - Z
t
RP
T6
ACT
Hi - Z
T7
Burst lengh = X
ACT
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