LM3S1150 Luminary Micro, Inc, LM3S1150 Datasheet - Page 114
LM3S1150
Manufacturer Part Number
LM3S1150
Description
Lm3s1150 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1150.pdf
(513 pages)
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Reset
Reset
Type
Type
System Control
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
114
Bit/Field
31:8
7
6
5
4
RO
RO
31
15
0
0
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
GPIOG
GPIOH
GPIOF
GPIOE
0
0
Name
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
reserved
GPIOH
R/W
RO
23
0
7
0
GPIOG
R/W
RO
22
0
6
0
GPIOF
R/W
RO
21
0
5
0
GPIOE
R/W
RO
20
0
4
0
GPIOD
R/W
RO
19
0
3
0
GPIOC
R/W
RO
18
0
2
0
July 26, 2008
GPIOB
R/W
RO
17
0
1
0
GPIOA
R/W
RO
16
0
0
0
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