LM3S1911 Luminary Micro, Inc, LM3S1911 Datasheet - Page 420

• Manufacturer Part Number: LM3S1911
• Description: Lm3s1911 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Electrical Characteristics
19.2.4
19.2.5
420
I
Table 19-12. I
a. Values depend on the value programmed into the TPR bit in the I
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
c. Specified at a nominal 50 pF load.
Figure 19-2. I
Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces to the device must be driven to 0 V
regulator controlled by HIB.
The external voltage regulators controlled by HIB must have a settling time of 250 μs or less.
Table 19-13. Hibernation Module AC Characteristics
Parameter
Parameter No.
Parameter No
2
C
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
A
LR
H1
H2
H3
I2CSDA
I1
I2
I3
I4
I5
I6
I7
I8
I9
I2CSCL
a
a
b
a
c
a
a
a
a
Parameter Name
Absolute accuracy low range
2
t
Parameter
2
2
WAKE_ASSERT
C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
Parameter
C Timing
C Characteristics
I1
t
t
t
HIB_HIGH
HIB_LOW
t
t
SCSR
t
t
SCH
t
t
t
t
SRT
SFT
SCS
DH
HT
DS
LP
Parameter Name
Start condition hold time
Clock Low period
I2CSCL/I2CSDA rise time (V
Data hold time
I2CSCL/I2CSDA fall time (V
Clock High time
Data setup time
Start condition setup time (for repeated start condition
only)
Stop condition setup time
Internal 32.768 KHz clock reference rising edge to /HIB asserted
Internal 32.768 KHz clock reference rising edge to /HIB deasserted
/WAKE assertion time
I2
I4
Min
-
Preliminary
Nom
-
DC
Parameter Name
Max
±1/4
I6
IH
IL
=2.4 V to V
=0.5 V to V
or powered down with the same external voltage
I7
Unit
LSB
2
C Master Timer Period (I2CMTPR) register; a TPR
IL
IH
=0.5 V)
=2.4 V)
I5
I8
Min
36
36
24
18
36
24
2
-
-
Nom
I3
9
-
-
-
-
-
-
-
-
(see note b)
Max
10
-
-
-
-
-
-
-
Min
62
-
-
Nom
200
July 26, 2008
30
system clocks
system clocks
system clocks
system clocks
system clocks
system clocks
system clocks
-
Max
Unit
I9
ns
ns
-
-
-
Unit
μs
μs
μs