LM3S1911 Luminary Micro, Inc, LM3S1911 Datasheet - Page 8

• Manufacturer Part Number: LM3S1911
• Description: Lm3s1911 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 309
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 310
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 310
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
8
Stellaris
CPU Block Diagram ......................................................................................................... 36
TPIU Block Diagram ........................................................................................................ 37
JTAG Module Block Diagram ............................................................................................ 47
Test Access Port State Machine ....................................................................................... 50
IDCODE Register Format ................................................................................................. 55
BYPASS Register Format ................................................................................................ 56
Boundary Scan Register Format ....................................................................................... 56
External Circuitry to Extend Reset .................................................................................... 58
Power Architecture .......................................................................................................... 60
Main Clock Tree .............................................................................................................. 62
Hibernation Module Block Diagram ................................................................................. 117
Clock Source Using Crystal ............................................................................................ 118
Clock Source Using Dedicated Oscillator ......................................................................... 119
Flash Block Diagram ...................................................................................................... 136
GPIO Port Block Diagram ............................................................................................... 161
GPIODATA Write Example ............................................................................................. 162
GPIODATA Read Example ............................................................................................. 162
GPTM Module Block Diagram ........................................................................................ 202
16-Bit Input Edge Count Mode Example .......................................................................... 206
16-Bit Input Edge Time Mode Example ........................................................................... 207
16-Bit PWM Mode Example ............................................................................................ 208
WDT Module Block Diagram .......................................................................................... 237
UART Module Block Diagram ......................................................................................... 261
UART Character Frame ................................................................................................. 262
IrDA Data Modulation ..................................................................................................... 264
SSI Module Block Diagram ............................................................................................. 301
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 304
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 304
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 305
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 305
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 306
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 307
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 307
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 308
I
I
START and STOP Conditions ......................................................................................... 339
Complete Data Transfer with a 7-Bit Address ................................................................... 340
R/S Bit in First Byte ........................................................................................................ 340
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 343
2
2
C Block Diagram ......................................................................................................... 338
C Bus Configuration .................................................................................................... 339
®
1000 Series High-Level Block Diagram ............................................................... 28
Preliminary
2
C Bus ............................................................... 340
July 26, 2008