LM3S6610 Luminary Micro, Inc, LM3S6610 Datasheet - Page 10

• Manufacturer Part Number: LM3S6610
• Description: Lm3s6610 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 14-8.
Figure 14-9.
Figure 14-10. Master Burst RECEIVE .................................................................................................. 355
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 356
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 357
Figure 14-13. Slave Command Sequence ............................................................................................ 358
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 17-6.
Figure 18-1.
Figure 18-2.
Figure 19-1.
Figure 19-2.
Figure 22-1.
Figure 22-2.
Figure 22-3.
Figure 22-4.
Figure 22-5.
Figure 22-6.
Figure 22-7.
Figure 22-8.
Figure 22-9.
Figure 22-10. JTAG TRST Timing ........................................................................................................ 534
Figure 22-11. External Reset Timing (RST) .......................................................................................... 535
Figure 22-12. Power-On Reset Timing ................................................................................................. 535
Figure 22-13. Brown-Out Reset Timing ................................................................................................ 535
Figure 22-14. Software Reset Timing ................................................................................................... 536
Figure 22-15. Watchdog Reset Timing ................................................................................................. 536
Figure 23-1.
Figure 23-2.
10
Master Single RECEIVE ................................................................................................. 353
Master Burst SEND ....................................................................................................... 354
Ethernet Controller Block Diagram .................................................................................. 383
Ethernet Controller ......................................................................................................... 383
Ethernet Frame ............................................................................................................. 385
Analog Comparator Module Block Diagram ..................................................................... 427
Structure of Comparator Unit .......................................................................................... 428
Comparator Internal Reference Structure ........................................................................ 429
PWM Unit Diagram ........................................................................................................ 439
PWM Module Block Diagram .......................................................................................... 440
PWM Count-Down Mode ................................................................................................ 441
PWM Count-Up/Down Mode .......................................................................................... 441
PWM Generation Example In Count-Up/Down Mode ....................................................... 442
PWM Dead-Band Generator ........................................................................................... 442
QEI Block Diagram ........................................................................................................ 475
Quadrature Encoder and Velocity Predivider Operation .................................................... 477
100-Pin LQFP Package Pin Diagram .............................................................................. 492
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 493
Load Conditions ............................................................................................................ 525
I
External XTLP Oscillator Characteristics ......................................................................... 530
Hibernation Module Timing ............................................................................................. 531
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 531
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 532
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 532
JTAG Test Clock Input Timing ......................................................................................... 533
JTAG Test Access Port (TAP) Timing .............................................................................. 534
100-Pin LQFP Package .................................................................................................. 537
108-Ball BGA Package .................................................................................................. 539
2
C Timing ..................................................................................................................... 527
Preliminary
July 25, 2008