LM3S2918 Luminary Micro, Inc, LM3S2918 Datasheet - Page 10

• Manufacturer Part Number: LM3S2918
• Description: Lm3s2918 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 385
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 386
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 387
Figure 15-13. Slave Command Sequence ............................................................................................ 388
Figure 16-1.
Figure 16-2.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 21-1.
Figure 21-2.
Figure 21-3.
Figure 21-4.
Figure 21-5.
Figure 21-6.
Figure 21-7.
Figure 21-8.
Figure 21-9.
Figure 21-10. External Reset Timing (RST) .......................................................................................... 504
Figure 21-11. Power-On Reset Timing ................................................................................................. 505
Figure 21-12. Brown-Out Reset Timing ................................................................................................ 505
Figure 21-13. Software Reset Timing ................................................................................................... 505
Figure 21-14. Watchdog Reset Timing ................................................................................................. 505
Figure 22-1.
Figure 22-2.
10
START and STOP Conditions ......................................................................................... 378
Complete Data Transfer with a 7-Bit Address ................................................................... 379
R/S Bit in First Byte ........................................................................................................ 379
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 382
Master Single RECEIVE ................................................................................................. 383
Master Burst SEND ....................................................................................................... 384
CAN Module Block Diagram ........................................................................................... 413
CAN Bit Time ................................................................................................................ 420
Analog Comparator Module Block Diagram ..................................................................... 453
Structure of Comparator Unit .......................................................................................... 454
Comparator Internal Reference Structure ........................................................................ 455
100-Pin LQFP Package Pin Diagram .............................................................................. 465
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 466
Load Conditions ............................................................................................................ 497
I
Hibernation Module Timing ............................................................................................. 500
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 501
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 501
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 502
JTAG Test Clock Input Timing ......................................................................................... 503
JTAG Test Access Port (TAP) Timing .............................................................................. 503
JTAG TRST Timing ........................................................................................................ 503
100-Pin LQFP Package .................................................................................................. 506
108-Ball BGA Package .................................................................................................. 508
2
C Timing ..................................................................................................................... 500
Preliminary
2
C Bus ............................................................... 379
July 26, 2008