LM3S2918 Luminary Micro, Inc, LM3S2918 Datasheet - Page 422
LM3S2918
Manufacturer Part Number
LM3S2918
Description
Lm3s2918 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S2918.pdf
(533 pages)
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Controller Area Network (CAN) Module
16.4.15.1 Example for Bit Timing at High Baud Rate
16.4.15.2 Example for Bit Timing at Low Baud Rate
422
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If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
The resulting configuration is written into the CAN Bit Timing (CANBIT) register :
(Phase_Seg2-1)&(Phase_Seg1+Prop_Seg-1)&(SynchronizationJumpWidth-1)&(Prescaler-1)
In this example, the frequency of CAN clock is 25 MHz, BRP is 0, and the bit rate is 1 Mbps.
t
delay of bus driver 50 ns
delay of receiver circuit 30 ns
delay of bus line (40m) 220 ns
tProp 640 ns = 16 × t
tSJW 160 ns = 4 × t
tTSeg1 800 ns = tProp + tSJW
tTSeg2 160 ns = Information Processing Time + 4 × t
tSync-Seg 40 ns = 1 × t
bit time 1000 ns = tSync-Seg + tTSeg1 + tTSeg2
tolerance for CAN_CLK 0.39 % =
In the above example, the parameters for the CANBIT register are: TSeg2=3, TSeg1=15, SJW =3
and BRP=0. This makes the final value programmed into the CANBIT register, 0x3FC0.
In this example, the frequency of CAN clock is 50 MHz, BRP is 25, and the bit rate is 100 Kbps.
t
delay of bus driver 200 ns
delay of receiver circuit 80 ns
delay of bus line (40m) 220 ns
tProp 4.5 ms = 9 × t
tSJW 2 ms = 4 × t
tTSeg1 6.5 ms = tProp + tSJW
tTSeg2 3 ms = Information Processing Time + 6 × t
tSync-Seg 500 ns = 1 × t
bit time 10 ms = tSync-Seg + tTSeg1 + tTSeg2
q
q
tbit = Bit Time
dfmax = Maximum difference between two oscillators
40 ns = 1/((BRP + 1) × CAN Clock)
500 ns = 1/((BRP + 1) × CAN clock)
min(PB1,PB2)/ 2 × (13 x bit time - PB2) =
0.1us/ 2 x (13x 1us - 2us)
q
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Preliminary
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July 26, 2008
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