LM3S2965 Luminary Micro, Inc, LM3S2965 Datasheet - Page 10

• Manufacturer Part Number: LM3S2965
• Description: Lm3s2965 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 391
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 392
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 393
Figure 15-13. Slave Command Sequence ............................................................................................ 394
Figure 16-1.
Figure 16-2.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 18-4.
Figure 18-5.
Figure 18-6.
Figure 19-1.
Figure 19-2.
Figure 20-1.
Figure 20-2.
Figure 23-1.
Figure 23-2.
Figure 23-3.
Figure 23-4.
Figure 23-5.
Figure 23-6.
Figure 23-7.
Figure 23-8.
Figure 23-9.
Figure 23-10. External Reset Timing (RST) .......................................................................................... 567
Figure 23-11. Power-On Reset Timing ................................................................................................. 568
Figure 23-12. Brown-Out Reset Timing ................................................................................................ 568
Figure 23-13. Software Reset Timing ................................................................................................... 568
Figure 23-14. Watchdog Reset Timing ................................................................................................. 568
Figure 24-1.
Figure 24-2.
10
START and STOP Conditions ......................................................................................... 384
Complete Data Transfer with a 7-Bit Address ................................................................... 385
R/S Bit in First Byte ........................................................................................................ 385
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 388
Master Single RECEIVE ................................................................................................. 389
Master Burst SEND ....................................................................................................... 390
CAN Module Block Diagram ........................................................................................... 419
CAN Bit Time ................................................................................................................ 426
Analog Comparator Module Block Diagram ..................................................................... 460
Structure of Comparator Unit .......................................................................................... 461
Comparator Internal Reference Structure ........................................................................ 462
PWM Unit Diagram ........................................................................................................ 472
PWM Module Block Diagram .......................................................................................... 473
PWM Count-Down Mode ................................................................................................ 474
PWM Count-Up/Down Mode .......................................................................................... 474
PWM Generation Example In Count-Up/Down Mode ....................................................... 475
PWM Dead-Band Generator ........................................................................................... 475
QEI Block Diagram ........................................................................................................ 509
Quadrature Encoder and Velocity Predivider Operation .................................................... 510
100-Pin LQFP Package Pin Diagram .............................................................................. 525
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 526
Load Conditions ............................................................................................................ 560
I
Hibernation Module Timing ............................................................................................. 563
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 564
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 564
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 565
JTAG Test Clock Input Timing ......................................................................................... 566
JTAG Test Access Port (TAP) Timing .............................................................................. 566
JTAG TRST Timing ........................................................................................................ 566
100-Pin LQFP Package .................................................................................................. 569
108-Ball BGA Package .................................................................................................. 571
2
C Timing ..................................................................................................................... 563
Preliminary
2
C Bus ............................................................... 385
July 25, 2008