LM3S2965 Luminary Micro, Inc, LM3S2965 Datasheet - Page 538

• Manufacturer Part Number: LM3S2965
• Description: Lm3s2965 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Signal Tables
538
QEI
SSI
Function
VBAT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD25
VDD25
VDD25
VDD25
VDDA
VDDA
WAKE
IDX0
IDX1
PhA0
PhA1
PhB0
PhB1
SSI0Clk
SSI0Fss
SSI0Rx
SSI0Tx
SSI1Clk
SSI1Fss
SSI1Rx
SSI1Tx
Pin Name
Number
100
Pin
55
20
32
44
56
68
81
93
14
38
62
88
98
50
84
25
37
83
36
28
29
30
31
72
73
74
75
8
3
Preliminary
Pin Type
I/O
I/O
I/O
I/O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
I
Buffer
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation Module power-source supply.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
An external input that brings the processor out of
hibernate mode when asserted.
QEI module 0 index
QEI module 1 index
QEI module 0 Phase A
QEI module 1 Phase A
QEI module 0 Phase B
QEI module 1 Phase B
SSI module 0 clock
SSI module 0 frame
SSI module 0 receive
SSI module 0 transmit
SSI module 1 clock
SSI module 1 frame
SSI module 1 receive
SSI module 1 transmit
Description
July 25, 2008