LM3311SQ National Semiconductor Corporation, LM3311SQ Datasheet - Page 18

• Manufacturer Part Number: LM3311SQ
• Description: Step-up Pwm Dc/dc Converter With Integrated Ldo, Op-amp, And Gate Pulse Modulation Switch
• Manufacturer: National Semiconductor Corporation

www.national.com
boost regulator and the LDO, so the ratio of the feedback re-
sistors sets the output voltage according to the following
equations:
SOFT-START CAPACITOR
The LM3311 has a soft-start pin that can be used to limit the
inductor inrush current on start-up. The external SS pin is
used to tailor the soft-start for a specific application (see the
Linear Regulator (LDO) section for the minimum value of
C
start capacitor C
V
THERMAL SHUTDOWN
The LM3311 includes thermal shutdown. If the die tempera-
ture reaches 145°C the device will shut down until it cools to
a safe temperature at which point the device will resume op-
eration. If the adverse condition that is heating the device is
not removed (ambient temperature too high, short circuit con-
ditions, etc...) the device will continue to cycle on and off to
keep the die temperature below 145°C. The thermal shut-
down has approximately 20°C of hysteresis. When in thermal
shutdown the boost regulator, LDO, Op-Amp, and GPM
blocks will all be disabled.
INPUT UNDER-VOLTAGE PROTECTION
The LM3311 includes input under-voltage protection (UVP).
The purpose of the UVP is to protect the device both during
start-up and during normal operation from trying to operate
with insufficient input voltage. During start-up using a ramping
input voltage the UVP circuitry ensures that the device does
not begin switching until the input voltage reaches the UVP
On threshold. If the input voltage is present and the shutdown
pin is pulled high the UVP circuitry will prevent the device from
switching if the input voltage present is lower than the UVP
On threshold. During normal operation the UVP circuitry will
disable the device if the input voltage falls below the UVP Off
threshold for any reason. In this case the device will not turn
back on until the UVP On threshold voltage is exceeded.
LINEAR REGULATOR (LDO)
The LM3311 includes a Low Dropout Linear Regulator. The
LDO is designed to operate with ceramic input and output ca-
pacitors with values as low as 2.2µF. The efficiency of the
LDO is approximately the output voltage divided by the input
voltage. When using higher input voltages special care should
be taken to not dissipate too much power and cause exces-
sive heating of the die. The power dissipated in the LDO
section is approximately:
The LDO has an output undervoltage lockout feature. This
feature is to ensure the LDO will shut itself down in the event
of an output overload or short condition. When the output is
overloaded the output voltage will fall causing the ADJ voltage
to fall. When the ADJ voltage falls to V
shut off. In this event the SHDN pin or the input UVP must be
cycled to turn the LDO back on.
SS
SS
. The soft-start time can be estimated as:
). When used, a current source charges the external soft-
SS
P
D(LDO)
until it reaches its typical clamp voltage,
T
SS
= (V
= C
SS
IN
*V
- V
SS
OUT
/I
SS
)*I
ADJ(LOW)
OUT
the LDO will
18
The LDO output undervoltage lockout is controlled by the SS
voltage. The LDO startup time must be less than the following:
When SS is less than 0.5V the output undervoltage lockout is
disabled and allows the LDO to start up. When SS is greater
than 0.5V the undervoltage lockout is active. If the LDO feed-
back voltage is not greater than V
0.5V the LDO may enter an undervoltage lockout condition.
In most cases C
other than that used to power V
must be taken to apply the input voltage to LV
plying voltage to V
OPERATIONAL AMPLIFIER
Compensation:
The architecture used for the amplifier in the LM3311 requires
external compensation on the output. Depending on the
equivalent resistive and capacitive distributed load of the
TFT-LCD panel, external components at the amplifier outputs
may or may not be necessary. If the capacitance presented
by the load is equal to or greater than an equivalent distibutive
load of 50Ω in series with 4.7nF no external components are
needed as the TFT-LCD panel will act as compensation itself.
Distributed resistive and capacitive loads enhance stability
and increase performance of the amplifiers. If the capacitance
and resistance presented by the load is less than 50Ω in se-
ries with 4.7nF, external components will be required as the
load itself will not ensure stability. No external compensation
in this case will lead to oscillation of the amplifier and an in-
crease in power consumption. A good choice for compensa-
tion in this case is to add a 50Ω in series with a 4.7nF capacitor
from the output of the amplifier to ground. This allows for driv-
ing zero to infinite capacitance loads with no oscillations,
minimal overshoot, and a higher slew rate than using a single
large capacitor. The high phase margin created by the exter-
nal compensation will guarantee stability and good perfor-
mance for all conditions.
Layout and Filtering considerations:
When the power supply for the amplifier (AV
to the output of the switching regulator, the output ripple of the
regulator will produce ripple at the output of the amplifiers.
This can be minimized by directly bypassing the AV
ground with a low ESR ceramic capacitor. For best noise re-
duction a resistor on the order of 5Ω to 20Ω from the supply
being used to the AV
you a cleaner supply to the amplifier. The bypass capacitor
should be placed as close to the AV
connected directly to the AGND plane.
For best noise immunity all bias and feedback resistors
should be in the low kΩ range due to the high input impedance
of the amplifier. It is good practice to use a small capacitance
at the high impedance input terminals as well to reduce noise
susceptibility. All resistors and capacitors should be placed
as close to the input pins as possible.
Special care should also be taken in routing of the PCB traces.
All traces should be as short and direct as possible. The out-
put pin trace must never be routed near any trace going to the
positive input. If this happens cross talk from the output trace
to the positive input trace will cause the circuit to oscillate.
The op-amp is not a three terminal device it has 5 terminals:
positive voltage power pin, AGND, positive input, negative in-
put, and the output. The op-amp "routes" current from the
power pin and AGND to the output pin. So in effect an opamp
has not two inputs but four, all of which must be kept noise
free relative to the external circuits which are being driven by
SS
IN
= 10nF or greater is sufficient. If a supply
.
T
IN
S
pin will create and RC filter and give
= C
SS
*0.5V/I
IN
is used to power LV
ADJ(LOW)
SS
IN
pin as possible and
when SS reaches
IN
) is connected
IN
prior to ap-
IN
IN
pin to
care