LM3311SQ National Semiconductor Corporation, LM3311SQ Datasheet - Page 23

• Manufacturer Part Number: LM3311SQ
• Description: Step-up Pwm Dc/dc Converter With Integrated Ldo, Op-amp, And Gate Pulse Modulation Switch
• Manufacturer: National Semiconductor Corporation

capacitor size can often be reduced. The size can also be
reduced if the input of the regulator is very close to the source
output. The size will generally need to be larger for applica-
tions where the regulator is supplying nearly the maximum
rated output or if large load steps are expected. A minimum
value of 10µF should be used for the less stressful condtions
while a 22µF to 47µF capacitor may be required for higher
power and dynamic loads. Larger values and/or lower ESR
may be needed if the application requires very low ripple on
the input source voltage.
The choice of output capacitors is also somewhat arbitrary
and depends on the design requirements for output voltage
ripple. It is recommended that low ESR (Equivalent Series
Resistance, denoted R
ramic, polymer electrolytic, or low ESR tantalum. Higher ESR
capacitors may be used but will require more compensation
which will be explained later on in the section. The ESR is also
important because it determines the peak to peak output volt-
age ripple according to the approximate equation:
A minimum value of 10µF is recommended and may be in-
creased to a larger value. After choosing the output capacitor
you can determine a pole-zero pair introduced into the control
loop by the following equations:
Where R
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be ne-
glected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section. Some suitable
capacitor vendors include Vishay, Taiyo-Yuden, and TDK.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90° in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than ½
the frequency of the RHP zero. This zero occurs at a fre-
quency of:
where I
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components R
and C
loop. Simply choose values for R
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:
C
LOAD
is to set a dominant low frequency pole in the control
L
is the minimum load resistance corresponding to
is the maximum load current.
ΔV
OUT
≊
ESR
2Δi
) capacitors be used such as ce-
L
R
ESR
C
(in Volts)
and C
C
within the ranges
C
23
where R
proximately 900kΩ. Since R
R
can be neglected until a value is chosen to set the zero f
f
capacitor, f
load currents as shown by the equation, so setting the zero is
not exact. Determine the range of f
and then set the zero f
dle. The frequency of this zero is determined by:
Now R
to make sure that the pole f
range, change each value slightly if needed to ensure both
component values are in the recommended range.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just
to improve the overall phase margin of the control loop, an-
other pole may be introduced to cancel the zero created by
the ESR. This is accomplished by adding another capacitor,
C
allel with the series combination of R
should be placed at the same frequency as f
The equation for this pole follows:
To ensure this equation is valid, and that C
without negatively impacting the effects of R
must be greater than 10f
CHECKING THE DESIGN
With all the poles and zeros calculated the crossover fre-
quency can be checked as described in the section DC Gain
and Open-loop Gain. The compensation values can be
changed a little more to optimize performance if desired. This
is best done in the lab on a bench, checking the load step
response with different values until the ringing and overshoot
on the output voltage at the edge of the load steps is minimal.
This should produce a stable, high performance circuit. For
improved transient response, higher values of R
chosen. This will improve the overall bandwidth which makes
the regulator respond more quickly to transients. If more detail
is required, or the most optimum performance is desired, refer
to a more in depth discussion of compensating current mode
DC/DC switching regulators.
POWER DISSIPATION
The output power of the LM3311 is limited by its maximum
power dissipation. The maximum power dissipation is deter-
mined by the formula
where T
(125°C), T
resistance of the package.
ZC
O
C2
, it does not have much effect on the above equation and
is created to cancel out the pole created by the output
, directly from the compensation pin V
C
jmax
O
can be chosen with the selected value for C
A
is the output impedance of the error amplifier, ap-
P1
is the ambient temperature, and θ
is the maximum specified junction temperature
. The output capacitor pole will shift with different
P
D
ZC
= (T
ZC
to a point approximately in the mid-
.
jmax
PC
C
is generally much less than
is still in the 10Hz to 500Hz
- T
P1
A
)/θ
over the expected loads
JA
C
C
and C
to ground, in par-
Z1
C2
JA
, the ESR zero.
C
is the thermal
can be used
and C
C
www.national.com
C
. The pole
should be
C
. Check
C
, f
PC2
ZC
.