LM3311SQ National Semiconductor Corporation, LM3311SQ Datasheet - Page 24

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LM3311SQ

Manufacturer Part Number
LM3311SQ
Description
Step-up Pwm Dc/dc Converter With Integrated Ldo, Op-amp, And Gate Pulse Modulation Switch
Manufacturer
National Semiconductor Corporation
Datasheet

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LAYOUT CONSIDERATIONS
The input bypass capacitor C
erating circuit, must be placed close to the IC. This will reduce
copper trace resistance which effects input voltage ripple of
the IC. For additional input voltage filtering, a 100nF bypass
capacitor can be placed in parallel with C
pin, to shunt any high frequency noise to ground. The output
capacitor, C
copper trace connections for the C
the series resistance, which directly effects output voltage
ripple. The feedback network, resistors R
be kept close to the FB pin, and away from the inductor, to
minimize copper trace connections that can inject noise into
the system. R
pins to minimize noise in the GPM circuitry. Trace connec-
tions made to the inductor and schottky diode should be
OUT
E
and C
, should also be placed close to the IC. Any
E
should also be close to the RE and CE
IN
, as shown in the typical op-
OUT
capacitor can increase
FB1
IN
, close to the V
and R
FB2
, should
IN
24
minimized to reduce power dissipation and increase overall
efficiency. For more detail on switching power supply layout
considerations see Application Note AN-1149: Layout Guide-
lines for Switching Power Supplies.
The input capacitor, output capacitor, and feedback resistors
for the LDO should be placed as close to the device as pos-
sible to minimize noise and increase stability. Keep the feed-
back traces short and connect R
to the device.
For Op-Amp layout please refer to the Operational Amplifier
section.
Figure 6, Figure 7, and Figure 8 in the Application Information
section following show the schematic and an example of a
good layout as used in the LM3310/11 evaluation board.
ADJ2
directly to AGND close

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