HMP8190CN Intersil Corporation, HMP8190CN Datasheet - Page 21
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HMP8190CN
Manufacturer Part Number
HMP8190CN
Description
NTSC/PAL Video Encoder
Manufacturer
Intersil Corporation
Datasheet
1.HMP8190CN.pdf
(32 pages)
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
BIT
7-0
7-0
7-0
7-0
1
0
FIELD Detect
Select
Field Detect
Window Size High
PHINC 0
(LSB)
PHINC 1
PHINC 2
PHINC 3
(MSB)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
21
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = odd field
1 = even field
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size
value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The
PHINC value is the phase increment value of the color subcarrier generation NCO. When the
BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to
determine the last PHINC value loaded via the selected interface.
TABLE 41. PHASE INCREMENT REGISTER 1
TABLE 42. PHASE INCREMENT REGISTER 2
TABLE 43. PHASE INCREMENT REGISTER 1
TABLE 40. PHASE INCREMENT REGISTER 0
TABLE 39. FIELD CONTROL REGISTER 2
HMP8190, HMP8191
SUB ADDRESS = 6B
SUB ADDRESS = 6C
SUB ADDRESS = 6D
SUB ADDRESS = 6E
SUB ADDRESS = 27
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
RESET
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
STATE
00
00
00
00
0
0
B
B
H
H
H
H