ATF22V10C ATMEL Corporation, ATF22V10C Datasheet - Page 5

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ATF22V10C

Manufacturer Part Number
ATF22V10C
Description
High Performance E2 PLD
Manufacturer
ATMEL Corporation
Datasheet

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t
Pin Capacitance
Note:
Power Down AC Characteristics
Notes: 1. Output data is latched and held.
Power Up Reset
The registers in the ATF22V10Cs are designed to reset
during power up. At a point delayed slightly from V
crossing V
The output state will depend on the polarity of the output
buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how V
lowing conditions are required:
Input Test Waveforms and
Measurement Levels
R
Symbol Parameter
, t
C
C
t
t
t
t
t
t
t
t
t
t
IVDH
GVDH
CVDH
DHIX
DHGX
DHCX
DLIV
DLGV
DLCV
DLOV
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F
IN
OUT
< 3 ns
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
2. HI-Z outputs remain HI-Z.
Valid Input Before PD High
Valid OE Before PD High
Valid Clock Before PD High
Input Don’t Care After PD High
OE Don’t Care After PD High
Clock Don’t Care After PD High
PD Low to Valid Input
PD Low to Valid OE
PD Low to Valid Clock
PD Low to Valid Output
RST
, all registers will be reset to the low state.
CC
actually rises in the system, the fol-
(f = 1 MHz, T = 25°C)
Typ
5
6
(1, 2, 3)
Min
5
0
0
(1)
CC
-5
Max
15
15
20
5
5
5
5
Max
1. The V
2. After reset occurs, all input and feedback setup times
3. The clock must remain stable during t
8
8
0.7V,
must be met before driving the clock pin high, and
3. Clock and input transitions are ignored.
CC
Min
7.5
0
0
rise must be monotonic, and starts below
-7
Output Test Loads:
Max
7.5
20
20
25
Units
7
7
7
pF
pF
Commercial
ATF22V10C
Min
10
0
0
Conditions
V
V
-10
IN
OUT
= 0V
PR
Max
= 0V
10
10
10
10
25
25
30
.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5

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