MT9045AN Zarlink Semiconductor, Inc., MT9045AN Datasheet
MT9045AN
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MT9045AN Summary of contents
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... DPLL Circuit Input TIE Impairment Monitor State Select Feedback HOLDOVER PCCi FLOCK RST Figure 1 - Functional Block Diagram Data Sheet Ordering Information MT9045AN 48 pin SSOP -40°C to +85°C T1/E1/OC3 System Synchronizer VDD VSS Output Interface Circuit State Select Frequency Select MUX FS1 ...
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MT9045 The MT9045 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and Stratum 4 and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander tolerance, jitter/wander ...
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Data Sheet Pin Description (continued) Pin # Name 7,17 V Positive Supply Voltage. +3.3V DD 28,35 8 OSCo Oscillator Master Clock (CMOS Output). connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For clock ...
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MT9045 Pin Description (continued) Pin # Name 30 PCCi Phase Continuity Control Input (Input). The signal at this pin affects the state changes between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and Secondary Normal Mode. The ...
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Data Sheet Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1 and Table 4. Frequency Select MUX Circuit The MT9045 operates with one of four possible input reference frequencies (8kHz, ...
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MT9045 During a switch from one reference to the other, the State Machine first changes the mode of the device from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate ...
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Data Sheet Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the jitter ...
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MT9045 Figure 5 - Output Interface Circuit Block Diagram The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock. The T1 and E1 signals are generated from a common DPLL signal. Consequently, all ...
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Data Sheet All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation section for full details. Master Clock The MT9045 can use either a clock or crystal as the master timing ...
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MT9045 From a reset condition, the MT9045 will take seconds (see AC Electrical Characteristics) of input reference signal to output signals which are synchronized (phase locked) to the reference input. The selection of input references is control ...
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Data Sheet MT9045 Measures of Performance The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output measured by applying ...
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MT9045 Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, ...
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Data Sheet Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and ...
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MT9045 Description Input Controls MS2 MS1 RSEL PCCi Legend Change / Not Valid MTIE State change occurs with TIE Corrector ...
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Data Sheet MT9045 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference within approximately 500 ms. MT9045 and Network Specifications The MT9045 fully meets all applicable PLL requirements (intrinsic jitter/wander, ...
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MT9045 ± For applications requiring 32ppm clock accuracy, the following clock oscillator module may be used. FOX F7C-2E3-20.0MHz Frequency: 20MHz Tolerance: 25ppm 0C to 70C Rise & Fall Time: 10ns (0.33V 2.97V 15pF) Duty Cycle: 40% to 60% The output ...
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Data Sheet The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal specification is ...
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MT9045 Lock Indicator The LOCK pin toggles at a random rate when the PLL is frequency locked to the input reference. In Figure 11 the RC-time-constant circuit can be used to hold the high state of the LOCK pin. Once ...
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Data Sheet MT9045 Lock A digital alternative to the RC-time-constant circuit is presented in Figure 12. The circuit in Figure 12 can be used to generate a steady lock signal. The circuit monitors the MT9045’s LOCK pin, as long as ...
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MT9045 Absolute Maximum Ratings* - Parameter 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 Storage temperature 5 48 SSOP package power dissipation * Exceeding these values may cause permanent damage. Functional operation under these ...
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Data Sheet AC Electrical Characteristics - Performance Characteristics 1 Freerun Mode accuracy with OSCi at Holdover Mode accuracy with OSCi at Capture range with OSCi at Phase lock time 11 Output ...
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MT9045 ALL SIGNALS t t IRF, ORF Figure 13 - Timing Parameter Measurement Voltage Levels AC Electrical Characteristics - Input/Output Timing PRI/SEC 8kHz PRI/SEC 1.544MHz PRI/SEC 2.048MHz PRI/SEC 19.44MHz F8o NOTES: 1. Input to output delay values are valid after ...
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Data Sheet Characteristics 1 Reference input pulse width high or low 2 Reference input rise or fall time 3 8kHz reference input to F8o delay 4 1.544MHz reference input to F8o delay 5 2.048MHz reference input to F8o delay 6 ...
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MT9045 F8o F0o F16o t C16o t C8o C4o C2o C6o C1.5o C19o F8o C2o RSP TSP 24 C16WL t C8W C8W t t C4W C4W t C2W t C6W t C6W t C15W t C19W t C19W Figure 15 ...
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Data Sheet F8o MS1,2, RSEL, PCCi Figure 17 - Input Controls Setup and Hold Timing AC Electrical Characteristics - Intrinsic Jitter Unfiltered Characteristics 1 Intrinsic jitter at F8o (8kHz) 2 Intrinsic jitter at F0o (8kHz) 3 Intrinsic jitter at F16o ...
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MT9045 AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered Characteristics 1 Intrinsic jitter (4Hz to 100kHz filter) 2 Intrinsic jitter (10Hz to 40kHz filter) 3 Intrinsic jitter (8kHz to 40kHz filter) 4 Intrinsic jitter (10Hz to 8kHz filter) † ...
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Data Sheet AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer Characteristics 1 Jitter attenuation for 1Hz@20UIpp input 2 Jitter attenuation for 1Hz@104UIpp input 3 Jitter attenuation for 10Hz@20UIpp input 4 Jitter attenuation for 60Hz@20UIpp input 5 Jitter ...
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MT9045 AC Electrical Characteristics - 2.048MHz Input to 2.048MHz Output Jitter Transfer Characteristics 1 Jitter at output for 1Hz@3.00UIpp input with 40Hz to 100kHz filter 2 3 Jitter at output for 3Hz@2.33UIpp input with 40Hz to 100kHz filter 4 5 ...
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Data Sheet AC Electrical Characteristics - 8kHz Input Jitter Tolerance Characteristics 1 Jitter tolerance for 1Hz input 2 Jitter tolerance for 5Hz input 3 Jitter tolerance for 20Hz input 4 Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz ...
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MT9045 AC Electrical Characteristics - 2.048MHz Input Jitter Tolerance Characteristics 1 Jitter tolerance for 1Hz input 2 Jitter tolerance for 5Hz input 3 Jitter tolerance for 20Hz input 4 Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz input ...
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Data Sheet 23. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz. 24. Jitter on reference input is less than 7nspp. 25. Applied jitter is sinusoidal. 26. Minimum applied input jitter magnitude to regain synchronization. 27. Loss of ...
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MT9045 32 Zarlink Semiconductor Inc. Data Sheet ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...