AD9859 Analog Devices, Inc., AD9859 Datasheet
AD9859
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AD9859 Summary of contents
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... Commercial and amateur radio exciter GENERAL DESCRIPTION OUT The AD9859 is a direct digital synthesizer (DDS) featuring a 10-bit DAC operating 400 MSPS. The AD9859 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform 200 MHz ...
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... AD9859—Electrical Specifications ................................................ 3 Absolute Maximum Ratings............................................................ 5 Pin Configuration............................................................................. 6 Pin Function Descriptions .............................................................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 11 Component Blocks ..................................................................... 11 Modes of Operation ................................................................... 16 Programming AD9859 Features............................................... 16 REVISION HISTORY Revision 0: Initial Version Serial Port Operation................................................................. 19 Instruction Byte .......................................................................... 21 Serial Interface Port Pin Description....................................... 21 MSB/LSB Transfers .................................................................... 21 Suggested Application Circuits..................................................... 23 Outline Dimensions ...
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... AD9859—ELECTRICAL SPECIFICATIONS Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND. Table 1. Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4× ...
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... Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9859 section). The longest time required is for the reference clock multiplier PLL to relock to the reference. The wake-up time assumes that there is no capacitor on DACBP and that the recommended PLL loop filter values are used ...
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... INPUTS DVDD_I/O IOUT IOUT INPUT AVOID OVERDRIVING MUST TERMINATE DIGITAL INPUTS. OUTPUTS TO AVDD. DO FORWARD BIASING NOT EXCEED THE ESD DIODES MAY OUTPUT VOLTAGE COUPLE DIGITAL NOISE COMPLIANCE RATING. ONTO POWER PINS. Figure 2. Equivalent Input and Output Circuits Rev Page AD9859 ...
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... Note that Pin 43, DVDD_I/O, can be powered to 1 3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only be powered to 1 DVDD 2 DGND 3 AVDD 4 AGND 5 AD9859 AVDD 6 TOP VIEW (Not to Scale) AGND Figure 3 ...
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... DAC. Input Pin Used as an External Power-Down Control (see Table 8 for details). Active High Hardware Reset Pin. Asserting the RESET pin forces the AD9859 to the initial state, as described in the I/O port register map. Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is returned low. If unused, ground this pin ...
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... AD9859 TYPICAL PERFORMANCE CHARACTERISTICS RBW 10kHz DELTA [T1] REF LVL VBW 10kHz –65.10dB –5dBm SWT 98.19639279MHz 0 1 –10 –20 –30 –40 –50 –60 1 –70 –80 –90 –100 CENTER 100MHz 20MHz/ Figure MHz FCLK = 400 MSPS, WBSFDR OUT RBW 10kHz DELTA [T1] ...
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... SPAN 2MHz CENTER 159.08MHz Figure 15. F Rev Page AD9859 RBW 1kHz RF ATT 20dB DELTA [T1] VBW 1kHz –81.71dB SWT 5s UNIT –601.20240481kHz 1 1 200kHz/ SPAN 2MHz = 80.3 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz ...
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... AD9859 Figure 16. Residual Phase Noise with F = 159.5 MHz, F OUT (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue) = 400 MSPS Figure 17. Residual Phase Noise with F CLK 4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue) Rev Page 9.5 MHz 400 MSPS (Green), OUT ...
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... With the on-chip oscillator enabled, users of the AD9859 connect an external crystal to the REFCLK and REFCLKB inputs to produce a low frequency reference clock in the range of 20 MHz to 30 MHz. The signal generated by the oscillator is buffered before it is delivered to the rest of the chip. This buffered signal is available via the CRYSTAL OUT pin. Bit CFR1< ...
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... The interface allows read/write access to all registers that configure the AD9859. MSB first or LSB first transfer formats are supported. ) The AD9859’s serial interface port can be configured as a single pin SET I/O (SDIO), which allows a 2-wire interface or two unidirectional pins for in/out (SDIO/SDO), which in turn enables a 3-wire inter- face ...
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... Load ARR OSK @ I/O UD Enable VCO Charge Pump Current Range <1:0> High Hardware CRYSTAL Speed Manual OUT Pin Sync Sync Active Enable Enable AD9859 (LSB) Default Bit 0 Value 0x00 Not Used 0x00 LSB First 0x00 0x00 Auto OSK Keying 0x00 0x00 Not Used ...
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... AD9859 Control Register Bit Descriptions Control Function Register No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9859. The functionality of each bit is detailed below. CFR1<31:27>: Not Used CFR1<26>: Amplitude Ramp Rate Load Control Bit CFR1<26> (default). The amplitude ramp rate timer is loaded only upon timeout (timer == 1) and is not loaded due to an I/O UPDATE input signal ...
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... CFR1<0>: Not Used, Leave at 0 Control Function Register No. 2 (CFR2) The CFR2 is used to control the various functions, features, and modes of the AD9859, primarily related to the analog sections of the chip. CFR2<23:12>: Not Used CFR2<11>: High Speed Sync Enable Bit CFR2< ...
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... I/O UPDATE until the appropriate auto-clear control bit is cleared. Shaped On-Off Keying The shaped on-off keying function of the AD9859 allows the user to control the ramp-up and ramp-down time of an on-off emission from the DAC. This function is used in burst trans- missions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. ° ...
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... TO DAC OSK ENABLE CFR<25> SYNC_CLK LOAD OSK TIMER 0 1 OSK PIN 0 HOLD OUT UP/DN INC/DEC ENABLE RAMP RATE TIMER AUTO SCALE FACTOR GENERATOR Figure 18. On-Off Shaped Keying, Block Diagram Rev Page CFR1<26> AMPLITUDE RAMP RATE REGISTER (ASF) LOAD DATA EN CLOCK AD9859 ...
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... The scale factors are synchronized to SYNC_CLK via the I/O UPDATE functionality. Synchronization; Register Updates (I/O UPDATE) Functionality of the SYNC_CLK and I/O UPDATE Data into the AD9859 is synchronous to the SYNC_CLK signal (supplied externally to the user on the SYNC_CLK pin). The I/O UPDATE pin is sampled on the rising edge of the SYNC_CLK. ...
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... AD9859s. In order to drive multiple AD9859s with one crystal, the CRYSTAL OUT pin of the AD9859 using the external crystal should be connected to the REFCLK input of the other AD9859. The CRYSTAL OUT pin is static until the CFR2<9> bit is set, enabling the output. The drive strength of the CRYSTAL OUT pin is typically very low, so this signal should be buffered prior to using it to drive any loads ...
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... All data input to the AD9859 is registered on the rising edge of SCLK. All data is driven out of the AD9859 on the falling edge of SCLK. Figure 21 through Figure 24 are useful in understand- ing the general operation of the AD9859 serial port. ...
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... I/O operation is complete. All data written to (read from) the AD9859 must be (is) in MSB first order. If the LSB mode is ac- tive, the serial port controller generates the least significant byte address first followed by the next greater significant byte ad- dresses until the I/O operation is complete ...
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... PWRDWNCTL = 0 CFR1<3> Don’t Care PWRDWNCTL = 1 CFR1<3> PWRDWNCTL = 1 CFR1<3> Table 8 indicates the logic level for each power-down bit that drives out of the AD9859 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation. Layout Considerations For the best performance, these layout guidelines should be observed ...
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... MODULATED/ DEMODULATED SIGNAL REFCLK SAW CRYSTAL REFCLK CRYSTAL OUT REFCLK VCO FREQUENCY TUNING WORD Figure 27. Two AD9859s Synchronized to Provide I and Q Carriers with Independent Phase Offsets for Nulling Rev Page AD9859 PHASE TUNING OFFSET WORD WORD 1 I/I BASEBAND IOUT LPF AD9859 DDS ...
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... ORDERING GUIDE Model Temperature Range AD9859YSV –40°C to +105°C AD9859YSV-REEL7 –40°C to +105°C AD9859/PCB © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. 9.00 BSC ...