AD9859 Analog Devices, Inc., AD9859 Datasheet - Page 11

• Manufacturer Part Number: AD9859
• Description: 400 Msps, 10-bit, 1.8 V Cmos Direct Digital Synthesizer
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
COMPONENT BLOCKS
DDS Core
The output frequency (f
frequency of the system clock (SYSCLK), the value of the
frequency tuning word (FTW), and the capacity of the accumu-
lator (2
f
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
In certain applications, it is desirable to force the output signal
to zero phase. Simply setting the FTW to 0 does not accomplish
this; it only results in the DDS core holding its current phase
value. Thus, a control bit is required to force the phase accumu-
lator output to zero.
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0). There-
fore, upon power-up, the phase accumulator remains clear until
the first I/O UPDATE is issued.
Phase-Locked Loop (PLL)
The PLL allows multiplication of the REFCLK frequency. Con-
trol of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register No. 2,
Bits <7:3>.
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK input
frequency by the corresponding decimal value. However, the
maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
Table 4. Clock Input Modes of Operation
CFR1<4>
Low
Low
Low
Low
High
S
defined as the frequency of SYSCLK.
f
O
=
32
f
in this case). The exact relationship is given below with
f
O
S
×
=
(
(
1
CLKMODESELECT
High
High
Low
Low
X
FTW
–
(
FTW
)
( )
f
S
2 /
O
) of the DDS is a function of the
2 /
32
32
)
)
with
with
2
0
31
CFR2<7:3>
3 < M < 21
M < 4 or M > 20
3 < M < 21
M < 4 or M > 20
X
≤
<
FTW
FTW
≤
<
2
31
2
32
–
1
Rev. 0 | Page 11 of 24
Oscillator Enabled?
Yes
Yes
No
No
No
Clock Input
The AD9859 supports various clock methodologies. Support for
differential or single-ended input clocks and enabling of an
on-chip oscillator and/or a phase-locked loop (PLL) multiplier
are all controlled via user programmable bits. The AD9859 may
be configured in one of six operating modes to generate the
system clock. The modes are configured using the CLKMODE-
SELECT pin, CFR1<4>, and CFR2<7:3>. Connecting the exter-
nal pin CLKMODESELECT to Logic High enables the on-chip
crystal oscillator circuit. With the on-chip oscillator enabled,
users of the AD9859 connect an external crystal to the REFCLK
and REFCLKB inputs to produce a low frequency reference
clock in the range of 20 MHz to 30 MHz. The signal generated
by the oscillator is buffered before it is delivered to the rest of
the chip. This buffered signal is available via the CRYSTAL
OUT pin. Bit CFR1<4> can be used to enable or disable the
buffer, turning on or off the system clock. The oscillator itself is
not powered down in order to avoid long startup times associ-
ated with turning on a crystal oscillator. Writing CFR2<9> to
Logic High enables the crystal oscillator output buffer. Logic
Low at CFR2<9> disables the oscillator output buffer.
Connecting CLKMODESELECT to Logic Low disables the
on-chip oscillator and the oscillator output buffer. With the
oscillator disabled, an external oscillator must provide the
REFCLK and/or REFCLKB signals. For differential operation,
these pins are driven with complementary signals. For single-
ended operation, a 0.1 µF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V. In
addition, the PLL may be used to multiply the reference
frequency by an integer value in the range of 4 to 20. Table 4
summarizes the clock modes of operation. Note that the PLL
multiplier is controlled via the CFR2<7:3> bits, independent of
the CFR1<4> bit.
System Clock
F
F
F
F
F
CLK
CLK
CLK
CLK
CLK
= F
= F
= F
= F
= 0
OSC
OSC
OSC
OSC
× M
× M
Frequency Range (MHz)
80 < F
20 < F
80 < F
10 < F
N/A
CLK
CLK
CLK
CLK
< 400
< 30
< 400
< 400
AD9859