AD9212BCPZRL7-65 Analog Devices, Inc., AD9212BCPZRL7-65 Datasheet - Page 31

• Manufacturer Part Number: AD9212BCPZRL7-65
• Description: Octal, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
• Manufacturer: Analog Devices, Inc.

SCLK
Table 14. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
SDIO
DS
DH
CLK
S
H
HI
LO
EN_SDIO
DIS_SDIO
CSB
DON’T CARE
DON’T CARE
t
S
R/W
Timing (minimum, ns)
5
2
40
5
2
16
16
1
5
t
DS
W1
W0
t
DH
A12
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
A11
t
0
HI
Description
Set-up time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Set-up time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 72)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 72)
10
NUMBER OF SDIO PINS CONNECTED TOGETHER
A10
20
t
Figure 72. Serial Timing Details
LO
Figure 71. SDIO Pin Loading
A9
30
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t
CLK
40
A8
50
A7
60
70
80
D5
90
D4
100
D3
D2
D1
D0
t
H
DON’T CARE
AD9212
DON’T CARE