AD9212BCPZRL7-65 Analog Devices, Inc., AD9212BCPZRL7-65 Datasheet - Page 6
![no-image](/images/no-image-200.jpg)
AD9212BCPZRL7-65
Manufacturer Part Number
AD9212BCPZRL7-65
Description
Octal, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9212BCPZRL7-65.pdf
(56 pages)
- Current page: 6 of 56
- Download datasheet (3Mb)
AD9212
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
4
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Can be adjusted via the SPI interface.
Measurements were made using a part soldered to FR4 material.
t
SAMPLE
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data to Data Skew
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
(t
/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
2
DATA-MAX
1
F
R
) (20% to 80%)
− t
) (20% to 80%)
DATA-MIN
A
)
PD
DATA
2
FRAME
, 3
)
)
)
EL
4
EH
)
)
)
FCO
4
CPD
)
)
4
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
Temp
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Min
40
1.5
1.5
(t
(t
SAMPLE
SAMPLE
/20) − 300
/20) − 300
AD9212-40
Typ
12.5
12.5
2.3
300
300
2.3
t
(t
(t
(t
±50
600
375
8
750
<1
1
FCO
SAMPLE
SAMPLE
SAMPLE
+
Rev. 0 | Page 6 of 56
/20)
/20)
/20)
Max
10
3.1
3.1
(t
(t
±200
SAMPLE
SAMPLE
/20) + 300
/20) + 300
Min
65
1.5
1.5
(t
(t
SAMPLE
SAMPLE
/20) − 300
/20) − 300
AD9212-65
Typ
7.7
7.7
2.3
300
300
2.3
t
(t
(t
(t
±50
600
375
8
750
<1
1
FCO
SAMPLE
SAMPLE
SAMPLE
+
/20)
/20)
/20)
Max
10
3.1
3.1
(t
(t
±200
SAMPLE
SAMPLE
/20) + 300
/20) + 300
Unit
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ns
μs
CLK
cycles
CLK
cycles
MSPS
ps
ps
ps rms
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