ZEN2044F Zenic, ZEN2044F Datasheet - Page 6

• Manufacturer Part Number: ZEN2044F
• Description: 33MHz Up/down Counter
• Manufacturer: Zenic

www.DataSheet4U.com
4. Operation
4-1. CPU Interface
4-1-1. Direct Channel Enable Mode(DRCTCE="1")
to specify "command words","counter reference value(if necessary)" and "preloaded value(if necessary)".
Since the entire control circuit woks synchronously, the operations about registers(i.e. data read/write,
command write and status read) can be carried out even if the counter is working.
the counter and the registers.
The opration of the
Each channel can be programed separately because the
two modes for selecting the target channel. The mode depends on DRCTCE.
The CPU can access the
DRCTCE
be accessd at a time(write operation only).
In this mode, AD/CE is used as the channel enable input for channel
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AD/CE3
1
1
1
1
0
0
1
1
1
0
0
*
*
*
*
*
*
ZEN2044F
AD/CE2
1
1
1
0
1
*
*
0
*
1
1
0
1
*
*
0
*
n
ZEN2044F
AD/CE1
is controled by the system software. To use this counter, it is necessary
1
1
0
1
1
*
0
*
*
1
0
1
1
*
0
*
*
with AD/CE3-0, C/D, RD and WR. The
AD/CE0
1
0
1
1
1
0
0
1
1
1
0
*
*
*
*
*
*
Table 2
C/D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*
- 6 -
RD
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
*
ZEN2044F
WR
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
*
Disable(data bus: High-impedance)
Read: latch register(ch.0)
Read: latch register(ch.1)
Read: latch register(ch.2)
Read: latch register(ch.3)
Write: data for registers(ch.0)
Write: data for registers(ch.1)
Write: data for registers(ch.2)
Write: data for registers(ch.3)
Read: status register(ch.0)
Read: status register(ch.1)
Read: status register(ch.2)
Read: status register(ch.3)
Write: command(ch.0)
Write: command(ch.1)
Write: command(ch.2)
Write: command(ch.3)
has four fully independent sets of
n
ZEN2044F
. So multiple channels can
Function
(
Z2044G00 ZENIC INC.
has following
ZEN2044F
)